Product category: Design and Development Software
News Release from: Altera Europe | Subject: Quartus II
Edited by the Electronicstalk Editorial Team on 9 December 2004
Design software optimises power management
Altera Corp is shipping version 4.2 of its Quartus II design software, delivering the world's highest performance for FPGAs and CPLDs
Quartus II software version 4.2 delivers an average of 39% higher performance on 90nm Stratix II FPGAs when compared with Virtex-4, 60% on 90nm Cyclone II FPGAs when compared with Spartan-3, and 50% on Max II CPLDs when compared with CoolRunner-II. 'Quartus II software delivers clear performance leadership, as well as superior ease of use', said Chris Balough, Altera's Director of Software and Tools Marketing.
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FPGA design software doubles productivity
Altera claims its latest software helps designers achieve more than 2x faster compile times and half the memory footprint of the nearest high-end FPGA
FPGA designers gain ASIC-strength toolset
Quartus II software is shipping with TimeQuest timing analyser, the first timing analysis tool from an FPGA vendor to provide comprehensive native support for the SDC timing format
'It's no surprise that Altera's design-win momentum is accelerating and why Quartus II software received the first annual FPGA and Programmable Logic Journal reader's choice award as the industry's best programmable logic development software'.
With this latest version of Quartus II software, Altera introduces the PowerPlay technology suite, the industry's most advanced tools for programmable logic power analysis and optimisation.
The analysis features included in the PowerPlay suite offer detailed estimates of static and dynamic power, and assist a designer during the entire design cycle, from design conception through implementation.
Further reading
Software increases FPGA designer productivity
The latest version of Altera's Quartus II includes design support for the new Stratix II GX FPGA family and new tools for increasing designer productivity
Designers can use the PowerPlay early power estimator spreadsheet at the outset of a project to estimate static and dynamic power consumption.
During the implementation phase, designers can refine power estimations by using the new PowerPlay power analyser tool, which improves estimation accuracy by combining an advanced 'vectorless power analysis' algorithm with place-and-route results.
If optional functional simulation vectors or gate-level simulation vector input are also used, designers can expect even more accurate estimations.
The PowerPlay analyser tool also offers the industry's most detailed insight into a design's power consumption profile, allowing a designer to scrutinise total power by design resource or hierarchy.
Armed with this data, designers can quickly target optimisation efforts to meet power budgets.
Throughout 2005, additional features will be added to the PowerPlay suite, including automated optimisation tools.
The PowerPlay power optimisation tools will provide designers with an efficient, automated way to optimise power consumption in FPGA, CPLD, and structured ASIC designs.
In addition to the new PowerPlay technology, version 4.2 also includes over 100 new features and enhancements to support advanced FPGA, CPLD, and structured ASIC designs.
New implementation and timing analysis features analyse and control clock skew and data skew, allow designers to model clock jitter, and enable better analysis and optimisation of register control signals.
SOPC Builder includes new features to support effortless integration of systems with components operating in multiple clock domains.
RTL-to-gates formal verification supports new RTL-to-gates functional equivalency checking with the Cadence Conformal LEC formal verification software.
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