Product category: Programmable Logic Devices
News Release from: Altera Europe | Subject: Quartus II
Edited by the Electronicstalk Editorial Team on 09 May 2006
FPGA designers gain ASIC-strength
toolset
Quartus II software is shipping with TimeQuest timing analyser, the first timing analysis tool from an FPGA vendor to provide comprehensive native support for the SDC timing format.
Altera is shipping version 6.0 of its Quartus II software Included in this version is TimeQuest timing analyser, the first timing analysis tool from an FPGA vendor to provide comprehensive native support for the industry-standard Synopsys Design Constraints (SDC) timing format
This article was originally published on Electronicstalk on 27 May 2008 at 8.00am (UK)
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Software upgrade provides speed boost
Customers using the 8.0 release to design Altera's 65nm Stratix III FPGAs on Windows platforms will see compile times reduced by up to 50%.
Software speeds compiling
A Quartus II software user working with a multiprocessor computer will experience, on average, a 20% reduction in compile times over single-processor computers.
The newest version also includes an expanded team-based design feature that efficiently manages team collaboration of high-density designs.
These advancements address the requirements of today's high-density 90and#8209;nm designs while laying the groundwork for meeting customers' needs