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Product category: Programmable Logic Devices
News Release from: Altera Europe | Subject: Stratix II FPGAs
Edited by the Electronicstalk Editorial Team on 3 February 2004

Adaptable architecture speeds
new FPGA generation

Featuring the industry's first adaptable FPGA architecture, Stratix II FPGAs offer more than double the logic density in a single device and are 50% faster than first-generation Stratix devices

Featuring the industry's first adaptable FPGA architecture, Stratix II FPGAs offers more than double the logic density in a single device and are 50% faster than first-generation Stratix devices. This latest generation of Altera's high-density FPGA architecture is 25% more efficient than first-generation Stratix devices, allowing designers to pack more functionality into less logic area.

The combination of the 90nm manufacturing process and a highly efficient architecture enables maximum integration, resulting in dramatic cost reductions when compared to previous high-density architectures.

"This is a huge breakthrough for the FPGA industry-the first we've seen in over a decade.

The new capabilities made possible by the move to 90nm are brilliantly outlined in Altera's new Stratix II family", said Rich Wawrzyniak, Senior Market Analyst, ASIC and SoC, Semico Research Corp.

"The availability of a flexible input structure allows designers to concurrently optimise critical path performance and minimise cost of the overall system".

"The introduction of the new Stratix II architecture signifies what is possibly the FPGA industry's biggest breakthrough in the past decade", said Ken McElvain, Chief Technology Officer at Synplicity.

"With Synplicity's ability to apply high level synthesis algorithms, our design tools are highly tuned to maximising the performance of the new architecture.

I predict that this new family will turn the tide for many ASIC designers who have been waiting for high density FPGAs to meet their performance, integration and cost needs".

The availability of the 90nm process technology presented both challenges and opportunities to build a more efficient architecture.

As Altera's engineers worked with customers during the product planning phase of the new family, they also took a closer look at the basic logic structure.

Immediately, it became clear that for high-density designs, the nearly 15-year-old, four-input look-up table (LUT) structure was becoming restrictive and imposed unnecessary performance and cost constraints on customers.

Consequently, a new logic structure was developed and dubbed "adaptive logic module" (ALM), allowing logic to be shared among adjacent logic functions.

"We set out on a path of true innovation and as a result, we've developed a new FPGA architecture that is truly unique in the industry", said John Daane, Altera's President, CEO and Chairman.

With up to eight inputs to the combinational logic block, one ALM can implement up to two independent functions each of varying widths, including any function of up to six-inputs and certain seven-input functions.

Each ALM also contains two programmable registers, two adders, a carry chain, an adder tree chain, and a register chain that make more efficient use of device logic capacity.

This innovative new logic building block delivers more logic capacity in a smaller physical area, provides faster device performance, and is 2.5 times more powerful than logic structures used in previous FPGA architectures.

Stratix II devices have more than twice the logic of Stratix FPGAs with the equivalent of close to 180,000 logic elements (LEs).

"Complementing the brand new logic structure, Stratix II devices include features that were a hit with customers of the original award-winning Stratix devices", said Erik Cleage, Altera's Senior Vice President of Marketing.

"These features include TriMatrix memory, DSP blocks and external memory interfaces".

Optimised for the 90nm process, the performance of of a number of features is significantly enhanced.

With over twice the density and more than 9Mbit of memory, the Stratix II device family runs 50% faster than previous-generation FPGAs.

Stratix II devices deliver fast, predictable performance for the most complex digital signal processing (DSP) functions with up to 384 18 x 18bit multipliers per device, while supporting 370MHz performance for high-bandwidth parallel processing.

Stratix II devices support the latest external memory interfaces in dedicated circuitry, including 266MHz DDR2 SDRAM, 300MHz RLDRAM II and 200MHz QDRII SRAM devices with sufficient bandwidth and I/O pins to support interfacing with multiple, standard 64bit, 168-/144-pin dual inline memory modules (DIMMs).

The embedded serialisation/deserialisation (serdes) and dynamic phase alignment (DPA) circuitry in Stratix II FPGAs enables 1Gbit/s source-synchronous I/O performance without consuming logic resources, while at the same time simplifying PCB layout and timing management for high-speed data transfer.

Stratix II devices offer up to 9Mbit of memory per device with parity bit capability to support a variety of memory-intensive applications.

Stratix II devices also include innovative new features such as advanced encryption standard (AES)-based, nonvolatile 128bit encryption technology.

This encryption technology ensures that a customer's intellectual property (IP) that is designed into a Stratix II FPGA is secure from piracy.

Stratix II devices are the first SRAM FPGAs with a nonvolatile encryption key.

"Stratix II devices expand FPGA functionality and performance well beyond traditional markets and applications", said Cleage.

"Its many architectural breakthroughs embody our commitment to continuous innovation".

Stratix II devices are supported by the Quartus II version 4.0 design software, the industry's most advanced design software.

Developed with many new ASIC-like design capabilities, the Quartus II design software offers customers a comprehensive suite of synthesis, optimisation, verification, and system-level design tools in a single, unified design environment.

Altera also offers off-the-shelf IP cores optimised for Stratix II devices.

Stratix II devices will also be available in the HardCopy structured ASIC version, giving customers a unique, seamless migration path to volume production not offered by any other semiconductor company.

HardCopy devices for Stratix II FPGAs increase performance and reduce power consumption compared to the FPGA implementation.

Engineering samples of the first member of the Stratix II device family, the EP2S60, will be available in Q2 2004.

Volume prices at the end of 2004 start at $125 in 25,000 unit volumes.

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