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Product category: Intellectual Property Cores
News Release from: Actel Europe | Subject: CoreU1LL, CoreU1PHY and CoreU2PHY DirectCores
Edited by the Electronicstalk Editorial Team on 18 April 2003

ATM cores are frugal with FPGA gates

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Actel has released three further intellectual property building blocks optimised for use with its reprogrammable, Flash-based ProASIC Plus and high-speed, antifuse-based Axcelerator FPGAs.

Actel has released three further intellectual property (IP) building blocks optimised for use with its reprogrammable, Flash-based ProASIC Plus and high-speed, antifuse-based Axcelerator FPGAs Developed, verified and supported by Actel, the new Utopia CoreU1LL, CoreU1PHY and CoreU2PHY DirectCores are targeted at asynchronous transfer mode (ATM) communication system developers for their next-generation ATM local area network (LAN) and ATM over Sonet/SDH applications, as well as virtual private networks (VPN), frame-relay backbones and residential broadband networks