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News Release from: Accellera
Edited by the Electronicstalk Editorial Team on 4 July 2002

Verilog extension adds behavioural design

SystemVerilog 3.0 has been approved as an Accellera standard

SystemVerilog extends the Verilog Hardware Description Language (HDL) to support architectural and behavioural design and system verification with assertions. "SystemVerilog represents the most significant advancement to the Verilog language, since its acceptance as an IEEE standard", said Dennis Brophy, Accellera Chairman.

"It takes Verilog to the next abstraction level - the architecture and behavioural design of a system - and adds to it powerful assertions that allow designers and system architects to build and verify full systems".

"Accellera's SystemVerilog standard marks a dramatic enhancement in the Verilog language's capability for abstract design, as well as architectural modelling and assertion-based verification.

A high degree of user, tool developer and IEEE committee expertise was applied to the task of evolving Verilog to meet exploding design complexity with a robust and effective language standard", remarked Vassilios Gerousis, Accellera's Technical Committee Chairman.

"Advances in technology and growing design complexity have made it necessary to move HDLs to the next level to support system design.

As a founding member of Accellera, we are pleased to be part of this effort with other users and EDA tool suppliers and encourage design, verification engineers to adopt and deploy SystemVerilog", commented Shrenik Mehta, Sr Engineering Manager, Global Testability, Tools and Validation, Sun Microsystems.

SystemVerilog supports the built-in C types to provide a clear translation to and from C for better encapsulation and code compaction.

The C types also give users improved methods to create algorithmic models and advance the abstract syntax a designer can use to create efficient synthesisable code.

Other synthesis improvements include enhancements to the "always" block to avoid simulation and synthesis mismatches.

With SystemVerilog, designers can also specify intent with their simulation, synthesis and formal verification tools.

To enhance design verification, SystemVerilog adds four procedural assertions, which allows the designer to test Boolean expressions and perform an action based on the expression's (or sequence of expressions') value (true or false).

Assertions can be added to the design to document the assumptions made by the designer and to facilitate "white box" testing.

Assertions can also be outside the design, either in a testbench to check the response of the design to the stimulus, or to control a tool such as a stimulus generator or a model checker.

To improve modelling at the abstract level, SystemVerilog adds interfaces to help model the communication between blocks of a digital system.

Communication between blocks of a digital system is a critical area that can affect everything from the ease of RTL coding, to hardware-software partitioning to performance analysis to bus implementation choices and protocol checking.

SystemVerilog's interface construct was created to encapsulate the communication between blocks, allowing a smooth migration from abstract system-level design to lower-level register-transfer and structural views of the design.

By encapsulating the communication between blocks, the interface construct facilitates design reuse.

Co-Design Automation, a provider of electronic system simulation, donated its Superlog Extended Synthesisable Subset (ESS).

Co-Design Automation and Real Intent, a provider of formal functional verification systems, donated the Superlog Design Assertion language Subset (DAS).

Accellera's Verilog ++ and Assertions technical committees developed SystemVerilog.

An intense effort took place over the last year that was supported by users, Accellera members and EDA tool suppliers.

The next step is to prepare the specification for IEEE review.

The SystemVerilog Language Reference Manual (LRM) is available now from Accellera for US $100.00 for a hardcopy and free for PDF download.

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