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News Release from: Accellera
Edited by the Electronicstalk Editorial Team on 31 May 2007

Award recognises speedy standardisation work

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Stephen Bailey will receive the Accellera Technical Excellence Award at DAC for his work in leading the Unified Power Format standard from inception to its successful completion

Accellera has selected Stephen Bailey as the 2007 recipient of its annual Technical Excellence Award for his commitment to leading the Unified Power Format (UPF) standard from inception to its successful completion. The award will be presented at Accellera's Open Industry meeting during the Design Automation Conference (DAC) on Wednesday 6th June 2007.

'Stephen Bailey, our UPF Technical Subcommittee Chair, led us to the completion of an Accellera standard in record time, all the while working to gain broad industry support and adoption', said Shrenik Mehta, Accellera Chairman.

'He inspired the best from the committee he led, and his efforts raised the bar to a new height in terms of technical achievement for Accellera'.

An open standard for low-power design was requested by users at DAC in 2006, and was approved by the Accellera Board of Directors as a standard in February of this year.

Strong, collaborative participation by Accellera members and other dedicated companies resulted in an open standard that was developed in only 5 months.

Seven companies donated proven technology to Accellera, and the UPF technical subcommittee converged them into a single standard under Bailey's leadership.

The standard enables EDA tool interoperability for designing power applications, especially for wireless and handheld devices where power management is a critical factor.

It is publicly available for download at no charge from the Accelera website.

The UPF standard will be explained in Accellera's workshop: 'Design and verification of low power ICs', at DAC on Sunday 3rd June 2007.

Bailey will be among the experts presenting example-based usage of UPF and demonstrations of EDA tool support for the standard.

When power consumption is a key consideration in IC design, describing low-power design intent with Accellera's UPF improves the way complex integrated circuits can be designed, verified, and implemented.

The open standard permits all EDA tool providers to implement advanced tool features that enable the design of modern low-power ICs.

Starting at the register transfer level (RTL) and progressing into the detailed levels of implementation and verification, UPF facilitates an interoperable, multivendor tool flow and ensures consistency throughout the design process.

Engineers who design low-power ICs are the ultimate beneficiaries of the exceptional accomplishments of Bailey's Subcommittee.

Stephen Bailey is the Product Marketing Manager for Questa in the Design for Verification and Test group at Mentor Graphics.

He has been part of the EDA industry for over 15 years, and his career has provided the opportunity to experience virtually all facets of electronic design.

Bailey has served in several industry standards activities including VHDL IEEE1076 working group chair, Property Specification Language (PSL) IEEE1850 working group member, IEEE Design Automation Standards Committee Secretary, Accellera Unified Power Format Technical Subcommittee Chair, and Accellera Unified Coverage Interoperability Standard Technical Subcommittee member.

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