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Design and Development Software
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Verification suite speeds video kit to market
User application article Ross Video has successfully completed and shipped a major project using Synopsys' VCS verification solution to enable faster time to market and higher verification predictability.
News from Synopsys (7 July 2006)
Low power clocking software goes below 65nm
PowerCentric version 3 extends its 15-25% power reduction capabilities to support advanced variability-aware design flows at 65nm and below.
News from Azuro (7 July 2006)
Design kits support Malaysian fab options
A 14-day service for custom design kits helps designers take advantage of the new 0.25, 0.18 and 0.15um processes that available since X-Fab's recent merger with 1st Silicon.
News from EDA Solutions (6 July 2006)
Russian aerospace industry adopts environment
Esterel Technologies has entered into a strategic partnership with GosNIIAS, one of the most prestigious Russian aerospace institutes.
News from Esterel Technologies (5 July 2006)
Development tools speed CEM test turnaround
User application article Axis Electronics has invested in a full suite of boundary-scan development tools from JTAG Technologies.
News from JTAG Technologies (4 July 2006)
Verification family spans specification to signoff
Conquest and Ascent join Clock Intent Verification and PureTime to complete the EnVision formal verification product family.
News from Real Intent (4 July 2006)
Speedy simulator handles larger chip designs
The latest release of RedHawk-EV delivers at least 2x faster runtime performance and 40% less memory utilisation for full-chip dynamic power integrity compared with the previous version.
News from Apache Design Solutions (4 July 2006)
Extended physical synthesis speeds IC to market
User application article Sunplus Technology, a leading supplier of consumer ICs, has taped out a large high-density consumer design with Synopsys' IC Compiler next-generation physical implementation solution.
News from Synopsys (4 July 2006)
Architecture cuts handset chipset down to size
User application article Agere has completed the design and implementation on a next-generation, 90-nanometre, mobile handset chipset using the Cadence X Architecture and successfully taped it out.
News from Cadence Design Systems (3 July 2006)
CMOS sensor maker streamlines design process
Enovia MatrixOne's Synchronicity DesignSync has been selected by Advasense, a maker of high quality CMOS image sensor products for the mobile phone industry.
News from MatrixOne (3 July 2006)
Layout optimisation engine removes IC hotspots
A novel tool automatically optimises design tape-out data to eliminate lithography related hot spots.
News from Sagantec (3 July 2006)
Datatypes improve simulation performance
Arbitrary-bit-width datatypes enable algorithm, system and hardware designers to precisely model bit-true behaviour in C++ specifications while accelerating simulation speeds by 10-200x. Brochure available
News from Mentor Graphics UK (3 July 2006)
Toolset turns to Altera's embedded processor
A new Tasking VX-toolset is designed for Altera Corporation's Nios II family of embedded processors.
News from Altium (3 July 2006)
RTOS features in MCU evaluation kit
Enea and IAR Systems have partnered with Oki Electric to offer a new evaluation platform for Oki Electric's family of ARM-based ML67Q4050 and ML67Q4060 microcontrollers.
News from Enea Embedded Technology (3 July 2006)
Software supports latest industrial PowerPC
Kozio has announced support for AMCC's new PowerPC 405EZ networked industrial processor.
News from Kozio (3 July 2006)
Variant management software works with Simulink
Pure-systems has been accepted as a member of The MathWorks Connections Programme.
News from Software Acumen (3 July 2006)
Software support speeds European drag racers
TurboTools Corporation is sponsoring Funny Car race team the Velocity Performance Group.
News from TurboTools Corp (3 July 2006)
Timing and signal integrity analysis come together
A next-generation transistor-level static timing analysis solution delivers concurrent timing and signal integrity analysis to address emerging custom circuit design challenges.
News from Synopsys (3 July 2006)
Memory controller IP supports encounter synthesis
Cadence Design Systems has announced support for Cadence Encounter RTL Compiler global synthesis on Databahn memory controller products.
News from Denali Software (30 June 2006)
National Semiconductor selects Altium Designer
National Semiconductor Corporation has selected Altium Designer, the unified electronics design software, as its global standard for Electronic Computer-Aided Design (ECAD) softwar
News from Altium (30 June 2006)
High-speed design and signal integrity workshop
Ansoft UK will hold its High-Speed Design Forum on Tuesday 3 October, at its office in Basingstoke, Hampshire.
News from Ansoft Europe (30 June 2006)
Synopsys continues IC Compiler momentum
Synopsys has announced the 2006.06 release of IC Compiler, Synopsys' next-generation place-and-router
News from Synopsys (30 June 2006)
HDTV chip with Synopsys' IC Compiler taped out
Synopsys has announced that Micronas has taped out one of its advanced HDTV (high-definition television) chips using Synopsys' IC Compiler.
News from Synopsys (30 June 2006)
Toolkit speeds Blackfin speech applications
ClearSpeech voice technology software is now available as an embedded toolkit for LabView.
News from NCT Europe (29 June 2006)
Next-generation IC router thinks outside the grid
The Cadence Precision Router is a space-based, full-chip and block routing solution for advanced mixed-signal, analogue and custom digital designs.
News from Cadence Design Systems (29 June 2006)
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