Xilinx simplifies design flow for FPGA technology

Xilinx has released its fourth-generation partial reconfiguration design flow and improvements to its clock-gating technology that reduce dynamic block-RAM power consumption in Virtex-6 FPGA designs.

Designers can download ISE Design Suite 12.2 to take advantage of an simpler-to-use partial reconfiguration design flow as well as take further steps to reduce power consumption and overall system costs, according to the company.

In addition, a low-cost simulation solution for the embedded design flow is now available in the latest release of the ISE Design Suite.

Tom Feist, senior marketing director for the ISE Design Suite, said: 'As systems become more complex and designers are asked to do more with less, the adaptability of FPGAs has become a critical asset.

'Xilinx FPGAs have long supported partial reconfiguration and the flexibility to perform onsite programming and reprogramming.

'Today, however, the severity of the constraints on cost, board space and power consumption requires exceptionally efficient and economic design strategies to compete, which is why we've made the design flow easier,' he added.

Partial reconfiguration enables on-the-fly flexibility that can expand the capabilities of a single FPGA.

While operational, designers can reprogram regions of the FPGA with new functionality without compromising the integrity of the applications running in the remainder of the device.

For example, customers developing wired optical transport network solutions can achieve multi-port multiplexer/transponder capabilities using 30-45 per cent fewer resources, whereas software-defined radio solutions can dynamically exchange communication waveforms at the same time as other waveforms continue to operate, without interruption and the need for bigger or additional components.

Partial reconfiguration also enables designers to manage power consumption by swapping out high-power-consuming functions for more power-efficient functions when the highest performance is not required.

Xilinx said that its fourth-generation partial reconfiguration is easier to use as it has a more intuitive design flow and interface.

This includes an improved timing constraint and timing analysis flow, the automatic insertion of proxy logic to bridge static and reconfigurable partitions and full-design timing closure and simulation capabilities.

ISE 12 enables designers to target Virtex-4, Virtex-5 and Virtex-6 devices for partial reconfiguration applications.

To help customers make their designs more power efficient, Xilinx enhanced its intelligent clock-gating technology, which was made available through the acquisition of Pwrlite in summer 2009, to enable the lowering of block-RAM dynamic power.

Through a set of algorithms, ISE can automatically neutralise unnecessary logic activity.

This is a primary factor behind power dissipation as it enables power optimisations that were not applied at the RTL level to be implemented downstream after synthesis, thereby reducing overall dynamic power consumption by as much as 30 per cent.

Starting in ISE Design Suite 12.2, the intelligent clock-gating optimisation will also reduce power for dedicated RAM blocks in either simple- or dual-port mode.

These blocks provide several enables: an array enable, a write enable and an output register clock enable.

Most of these power savings will come from using the array enable.

The ISE FPGA tool suite offers fine-grain clock-gating optimisations integrated to the place and route algorithms.

A Xilinx white paper (WP370), entitled 'Reducing Switching Power with Intelligent Clock Gating', provides more information on this.

ISE Simulator (Isim) is now available for the embedded design flow through the Xilinx Platform Studio (XPS) and Project Navigator tools, enabling embedded designers to take advantage of the mixed language (VHDL and Verilog) simulator integrated with the ISE Design Suite.

The new version of Isim includes several productivity-enhancing features, such automatic detection and the listing of design memories for viewing and editing.

This new memory editor enables designers to explore what-if scenarios using a graphical method to force a value or a pattern on a signal without needing to recompile the design.

ISE 12 also makes it possible for designers to navigate to HDL source from the waveform viewer.

The software is rolling out in phases, with intelligent clock gating for Virtex-6 FPGA designs already shipping with the 12.1 release, partial reconfiguration for Virtex-6 FPGA designs starting in the 12.2 release and AXI4 IP support to follow in the 12.3 release.

The ISE 12 suite works with the latest simulation and synthesis software from Aldec, Cadence Design Systems, Mentor Graphics and Synopsys.

In addition, the ISE 12 software features an average of two times faster logic synthesis and 1.3 times faster implementation runtimes for large designs when compared with previous versions and an improved embedded design methodology.

ISE Design Suite 12.2 is immediately available for all ISE editions and is list priced starting at USD2,995 (GBP1,920) for the Logic Edition.

The fourth-generation partial reconfiguration can be purchased as an option and is bundled with two days of onsite training.

Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx website.

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