Novel methodology decimates SoC verification times

Verisity has developed a new methodology that enables a 10x increase in productivity and improved predictability for automating the verification process at the SoC and system level.

Verisity has developed a new methodology, and tightly coupled technology, that enables a 10x increase in productivity and improved predictability for automating the verification process at the SoC and system level.

The System Verification Methodology (sVM) encapsulates comprehensive guidelines that effectively transfer specialised verification expertise, while new technology in the Specman Elite verification process automation solution and library additions simplify adoption and enable productivity gains required for the largest nanometer era designs.

sVM provides productivity gains greater than 10x in the composition of SoC and system-level verification environments by raising the level of abstraction to the sequence level (combinations of transactions).

In addition, multichannel constraint solving and generation makes it possible to achieve the same coverage goals in one-tenth the number of verification cycles as compared with directed testing or other customised methods.

sVM-based environments provide for the generation of realistic, interdependent system scenarios using third-generation constraint-solver technology to fully meet coverage goals.

sVM leverages the combination of new technology in Specman Elite with new libraries that include multichannel and layered (hierarchical) sequences, a register model package, the Visualization Toolkit and other verification building blocks.

In addition, Verisity has also released eAnalyzer, a static analysis and verification methodology compliance system that aids engineers in codifying Verisity's e Reuse Methodology (eRM) and sVM, thus enabling verification component reuse, and easy creation of highly automated, high-quality, consistent chip and system-level verification environments.

The new releases represent another major step forward for Verisity's Verification Process Automation (VPA) strategy, going well beyond language and testbench toward automating and simplifying the increasingly complex process from executable test plans to verification closure.

Verisity's VPA solutions combine prepackaged, proven best practices with automation, analyses, and libraries in a form that can be readily adopted by the mainstream engineering community.

In contrast to verification infrastructure (such as simulators) that now have limited potential for performance improvements, VPA solutions offer the potential to dramatically shorten the most time consuming verification activities by a factor of ten.

sVM was developed based on the huge success of Verisity's e Reuse Methodology (eRM) and extends eRM's applicability to meet the unique and complex needs for chip, SoC and system-level verification.

sVM goes beyond just verification reuse by providing a methodology covering the complete verification process.

"We encapsulated best practices for verification reuse into eRM just over a year ago and it has been widely accepted within our customer base", said Steve Glaser, Vice President of Corporate Marketing and Business Development for Verisity.

"With sVM, we've taken best practices developed with our high-end customers doing SoC-level verification, and created a widely adoptable companion methodology to the eRM.

sVM and its enabling technologies deliver prepackaged expertise and 10x automation power to the broader community".

The evolution of increased chip-level verification complexity combined with limited verification expertise requires VPA solutions that go well beyond simulation infrastructure or variations of existing design and verification languages.

With sVM and its associated technology enhancements, Verisity provides a complete "out-of-the-box" solution that increases verification productivity and proliferates best practices.

Verification expertise has become so specialised, that companies are increasingly facing a shortage of engineers who can effectively define and manage the verification process.

sVM simplifies the adoption of proven SoC verification methodologies for a much broader range of engineers.

A supporting technology of sVM is multichannel and layered sequence generation.

Multichannel generation enables a new level of verification automation at the SoC and system levels.

Automated verification of SoCs requires a methodology and verification architecture that mirrors the architecture of the design itself.

Typically, SoCs have multiple I/Os and multiple on-chip buses linking many IP components.

Such devices need to be thoroughly exercised simultaneously from all possible interfaces to control and receive data.

This requires embedding of generators, checkers and monitors for each channel, as well as multichannel constraint solving, synchronisation and co-ordination.

This is the only proven way to introduce all possible scenarios and reach all corner cases at the SoC level.

Unfortunately, this is very difficult without new abstractions and automated support for specifying and generating system-level scenarios using independent yet co-ordinated sequences (groups of transactions).

It also requires specialised algorithms to ensure scalability of capacity, performance and time-to-verification closure.

"The process of applying random stimulus generation for SoC and chip-level verification has been fairly limited in the past due to the difficulty in creating realistic system-level scenarios and the limited scalability of verification algorithms", said Mike Stellfox, Worldwide Director of Consulting and Product Engineering for Verisity.

"With Specman Elite's new multichannel sequence generation technology, many leading-edge customers are now able to realise significant gains in efficiency for full-chip verification.

This new technology automates and simplifies the process of creating verification environments and stimulating their complete chip with critical, real-world traffic.

Multichannel sequence generation is clearly a key enabling technology for automating and proliferating the sVM process for SoC and chip-level verification".

sVM coupled with highly scaleable, multichannel generation technology also leverages environments built in multiple levels of hierarchy.

sVM's multichannel sequences also use block-level sequence stimulus, enabling them to be automatically combined, synchronised, and co-ordinated at the system level to simulate real-world conditions.

This allows simultaneous and coordinated stimulation of the device through all possible channels, with maximum intelligence and efficiency of verification cycles.

Using multichannel generation, Verisity's leading-edge customers have experienced more than a 10x increase in the automation power applied at the SoC and system level.

By raising the level of abstraction to the sequence level (combinations of transactions), it now takes one-tenth the time to compose and bring up SoC-level verification environments.

In addition, multichannel constraint solving and generation requires one-tenth the number of verification cycles to achieve the same coverage goals versus directed testing or other customised methods.

sVM also provides support for powerful register modelling and automated device configuration generation using a new register package.

sVM's register package provides a way to model, generate and check the configuration for the entire chip or SoC.

Today's complex chips are highly programmable and engineers need to verify that programmability.

sVM's register package provides the ability to model all device registers easily and efficiently, automatically generates configuration sequences, and automates much of the checking and coverage of register access and the device state.

It also allows users to map registers into address spaces, and handle address spaces in general.

Ultimately, by incorporating the register package, all verification components will use the same interface, which dramatically shortens the time it takes for verification environment creation.

To support the analysis portion of sVM, the Visualization Toolkit (VT) has been upgraded to support key aspects of the SoC-level verification process and environment.

VT provides visualisation and debugging of the multi-channel sequence generation transaction interactions, which greatly simplifies understanding and debugging chip-level environments.

It also includes a rich API for creating customised visualisation aids.

The updated library package which includes multichannel generation technology, the register model package and the new Visualization Tookit, and documentation, will be available with the full release of Specman Elite v4.3 scheduled for October 2003.

Limited release versions are available today.

All technology enhancements and sVM will be provided at no charge to Specman Elite customers.

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