News Release from: Verisity Design
Edited by the Electronicstalk Editorial Team on 26 March 2003
Verification components cover popular demand
Verisity is greatly expanding its offerings of eVerification Components (eVCs) in order to meet the increasing demand for reusable verification components for standard interfaces.
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Verisity is greatly expanding its offerings of eVerification Components (eVCs) in order to meet the increasing demand for reusable verification components for standard interfaces. With the growth in the number and complexity of system-on-chip and system-level designs, verification reuse has become a major focus for verification teams because of the benefits it provides - dramatic productivity and product quality gains. To support its customers, Verisity is delivering seven new eVerification Components for the most popular protocols: PCI/PCI-X, PCI Express, Gigabit Ethernet, SPI-4, Sonet, SDH and Fibre Channel.
All Verisity eVCs comply with the eReuse Methodology (eRMT) guidelines ensuring that they will interoperate and behave consistently with any other eRM-compliant eVCs.
Verisity pioneered verification reuse methodologies with the introduction of reusable verification components over two years ago.
eVCs are reusable, plug-and-play verification environments for standard protocols and interfaces and are based on Verisity's high-level verification language, e, and the Specman Elite testbench automation solution.
They comprise a complete verification environment following a coverage-driven verification (CDV) methodology and include constraint-driven test generation, data and assertion checking and functional coverage analysis.
CDV is a proven methodology that provides predictable, scalable results and is critical to achieving first-pass silicon success.
"eVCs have become a major part of our verification strategy", said Don Friedberg, Director of Design Methodologies for Agere Systems.
"They increase our productivity and are critical to achieving our goal of providing exceptional service with first-pass success to our customers".
To take full advantage of a CDV methodology, Verisity recently delivered the comprehensive verification reuse methodology, eRM, which standardises a method for encapsulating CDV methods for easy reuse.
Today's announcement makes Verisity a broad-line eVC supplier.
"In SoC, system and platform-based designs, standard interfaces abound", said Francine Ferguson, Vice President of Corporate and Strategic Marketing for Verisity.
"This is why customers are requiring multiple eVCs per project.
Verisity has chosen the most popular interfaces for its initial expansion and because they are eRM compliant, they are completely plug-and-play and allow users to implement true system-level verification".
Today's complex chips, systems and SoCs commonly incorporate many different protocols, interfaces and processors.
This surge in the number of protocols and interfaces per design has placed an extra burden on the verification team by requiring them to become experts in these standards in order to verify them within the context of their design.
eVCs have become widely popular among verification engineers because in addition to increasing their productivity, they drastically reduce the need for protocol expertise by delivering a complete verification environment for standards.
"Our designs encompass a multitude of standard interfaces and it's just not efficient for our verification engineers to develop new testbenches", said Ari Cohen, Vice President of Hardware Engineering and Operations for Silverback Systems.
"eVCs have changed all this for us.
By using eVCs, we're able to start verification much earlier and we are assured that we'll hit our corner cases because the eVCs have been proven before and were developed by engineers who have expertise in this area".
eVCs provide numerous advantages to verification teams including a major increase in productivity and higher quality products.
Engineers can create their verification environments in days instead of months, start simulation much earlier and complete verification faster.
eVCs can be easily moved from module-level to chip-level verification efforts as well as from design project to project, thereby enhancing a verification reuse methodology.
A variety of eVCs can be intermixed within a single verification environment.
To ensure that all eVCs plug-and-play and behave consistently, Verisity created the e Reuse Methodology (eRM), which defines the standards for architecting, coding and packaging eVCs as well as advanced methodologies for easy generation and synchronisation of complex system-level sequences.
Through eRM, the company is promoting best practices among eVC developers by providing comprehensive guidelines and best-known methods for eVC development.
The PCI/PCI-X, PCI Express, Gigabit Ethernet, SPI-4, Sonet, SDH and Fibre Channel eVCs will be available beginning in the second quarter of 2003.
The list price for a single floating, annual time-based licence is $10,000.
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