Product category: Intellectual Property Cores
News Release from: Virage Logic | Subject: Technology-Optimized Platform and ASAP Logic
Edited by the Electronicstalk Editorial Team on 26 March 2004
IP runs on latest Chartered/IBM 90nm
process
Virage Logic's Technology-Optimized Platform will be made available on the jointly developed Chartered Semicondutor Manufacturing and IBM 90nm manufacturing process.
Virage Logic's Technology-Optimized Platform - as well as its Area, Speed and Power (ASAP) Logic metal programmable cell libraries - will be made available on the jointly developed Chartered Semiconductor Manufacturing and IBM 90nm manufacturing process SoC designers can now benefit from seamless, easy access to Virage Logic's highly differentiated, silicon-proven intellectual property (IP) as part of the semiconductor industry's first common cross-foundry design enablement programme starting at 90nm, announced by IBM and Chartered
This article was originally published on Electronicstalk on 22 Oct 2002 at 8.00am (UK)
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