News Release from: Verplex Systems
Edited by the Electronicstalk Editorial Team on 23 September 2002

Verification seminar comes to Munich

The Verify 2002 committee has chosen Munich, Germany, as the location for this year's European seminar.

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The Verify 2002 committee has chosen Munich, Germany, as the location for this year's European seminar. Verify 2002 is a series of educational seminars on assertion-based verification in the intelligent testbench for SoC design. The series, which tours selected cities across the USA and Canada throughout October and November, arrives in Europe on 10th October 2002.

These educational seminars have been designed to help electronic engineers learn how to incorporate and use assertion-based languages and tools in their design flows and advance towards an intelligent testbench solution.

Each seminar includes two featured speakers.

Harry Foster, chairman of Accellera's Formal Language Committee and author of "Principles of verifiable RTL", and the soon-to-be-released "Assertion-based design", will present a tutorial on why, where and how to use assertions in IC designs.

Anders Nordstrom, director of engineering at PacketDNA and a member of the IEEE1364 Verilog Standards Committee and the Accellera SystemVerilog Committee, will take participants through the evolution of verification methodologies, and provide a real-world example of verification methodologies associated with advanced telecom designs.

Sponsor companies and presenters include: Axis Systems, CoWare, Denali Software, Forte Design Systems, Novas Software, Sun Microsystems and Verplex Systems.

Agenda sessions include: "An assertion methodology for emulation", by Axis Systems; "Transaction level hardware and software verification for SoCs", by CoWare; "Using memory-based assertions for system verification", by Denali Software; "Functional coverage and high-level SystemC modelling for RTL verification", by Forte Design Systems; "Debugging for the intelligent testbench", by Novas Software; "Intelligent resource management with SunGrid engine", by Sun Microsystems; and "An assertion-based formal methodology for functional closure", by Verplex Systems.

The Verify Seminars, which began in 1997, are free of charge to any design engineer, verification engineer or engineering manager.

To register, or find out further information on the dates and locations of seminars, visit www.verifyseminars.com.

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