News Release from: Verific Design Automation
Edited by the Electronicstalk Editorial Team on 30 November 2004
Parser brings SystemVerilog to mainstream EDA
Verific Design Automation is shipping the first commercially available SystemVerilog parser.
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Verific Design Automation is shipping the first commercially available SystemVerilog parser. Written in platform-independent C++ for easy integration, consistency and efficiency, Verific's SystemVerilog Parser supports the entire SystemVerilog 3.1 language definition, with the exception of SystemVerilog Assertions, for which it supports 3.1a. Since the SystemVerilog Parser began shipping on 1st October, early adopters have used it in formal verification software and HDL visualisation tools.
'The market is quickly moving to SystemVerilog and we respond immediately to market demands', says Rob Dekker, President of Verific.
'Supporting SystemVerilog with our SystemVerilog Parser gives EDA developers the means to support this powerful language inside their design tools, and hence providing a large group of end users, essentially design engineers, with access to the language'.
'If the end users want it, their EDA tools provider can now deliver'.
SystemVerilog, the hardware description and verification language (HDVL) standard, is an extension of the established IEEE1364-2001 Verilog language, and was developed by Accellera to improve productivity in the design of large gate count, intellectual property (IP)-based, bus-intensive chips.
It is targeted primarily at the chip implementation and verification flow, with links to the system-level design flow.
Verific's SystemVerilog Parser includes a parser, analyser and elaborator.
It parses and analyses the entire SystemVerilog 3.1 language definition.
For assertions, it follows the SystemVerilog 3.1a syntax.
After parsing, a complete parsetree is available.
Static elaboration and register transfer level (RTL) elaboration for synthesis is fully supported for the Verilog 2001 subset, extended with support for many of the new SystemVerilog constructs.
Additional elaboration is planned for intermediate releases between now and the end of the year, The parser has been tested with an internally developed SystemVerilog test suite, and has also been verified with simulators provided by partnerships with Synopsys and Mentor Graphics.
The SystemVerilog Parser is shipping now and runs on Solaris, HP-UX, Linux and Windows platforms.
The US list price starts at $100,000 for a perpetual, royalty-free source-code licence of the parser and analyser.
Pricing for a time-based licence starts at $4000 per month.
Additionally, Verific offers an upgrade programme for existing Verilog 2001 customers.
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