Click on the advert above to visit the company web site
Product category: Intellectual Property Cores
News Release from: Tensilica | Subject: Core-optimised IP Kits
Edited by the Electronicstalk Editorial Team on 14 December 2006
Kits optimised to meet area, performance
and power
Request your FREE weekly copy of the Electronicstalk email newsletter. News about Intellectual Property Cores and more every issue. Click here for details.
Tensilica and Virage Logic have jointly introduced 16 specially designed core-optimised IP Kits for Tensilica's Diamond Standard processor family members
Tensilica and Virage Logic, a pioneer in Silicon Aware IP and leading provider of semiconductor intellectual property (IP) platforms, have jointly introduced 16 specially designed core-optimised IP Kits for Tensilica's Diamond Standard processor family members for manufacture on TSMC's 130nm and 90nm G processes The new core-optimised IP Kits consist of Virage Logic's Area, Speed and Power (ASAP) Memory and ASAP Logic IP, and are optimised for each of the Diamond cores to allow designers to target area, performance or power