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Product category: Communications ICs (Wired)
News Release from: Texas Instruments (April 2001-March 2006) | Subject: TLK3118
Edited by the Electronicstalk Editorial Team on 18 March 2004

Serdes drives a bigger backplane

Anmerkung: Kostenlose Broschüren oder Kataloge zu den in diesen Pressemitteilungen aufgeführten Produkten sind erhältlich von Texas Instruments (April 2001-March 2006). Bitte hier klicken, um ein Exemplar anzufordern.

A new discrete serialiser/deserialiser (serdes) is capable of error-free transmission over 80in of standard backplane trace

Manufactured in TI's advanced 130nm CMOS technology, the TLK3118 is a flexible, redundant XAUI serial transceiver compliant with the IEEE802.3ae specification for 10 Gigabit Ethernet. Ideal for local, metropolitan and wide area network applications, the device enables designers to reduce board space and design time.

Within backplane designs, the TLK3118 enables higher port density systems by reducing board space, system costs and power consumption, ultimately packing more high-speed channels/ports in less space, in turn cutting costs for network service providers.

The device performs the parallel-to-serial conversion, serial-to-parallel conversion and clock extraction functions for a physical layer interface.

It provides a complete XGXS (10 Gigabit extended sublayer) function with a redundant serial (XAUI) port.

Redundancy is critical to communication equipment makers that want to provide systems with high availability and superior quality of service (QoS).

The serial transmitter is implemented using differential current mode logic with integrated termination resistors.

The device employs state-of-the-art transmit and receive equalisation technology for superior signal integrity over industry standard media such as FR4 backplanes.

This equalisation technology has enabled TI to achieve error-free data transmission over 80in of backplane with this device.

TI's advanced 130nm process technology enables TLK3118 to achieve extremely low power dissipation of 1.6W (with HSTL termination turned off) at 3.125Gbit/s.

The device has been developed using the proprietary serial link core technology within TI's 130nm standard cell library.

The use of common serial link core intellectual property across both ASIC and discrete serdes solutions provides customers the unique opportunity to choose between discrete and ASIC-based solutions as they incorporate TI's advanced serial link technology.

The capability to deliver both discrete and ASIC-based serial link solutions enables TI to service every phase of a customer's product life cycle with consistent and proven technology.

The TLK3118 is sampling now to partner customers, with planned production in 3Q04.

The device is packaged in a 21 x 21mm, 400-ball, 1mm-ball-pitch ball grid array (FC-BGA) package.

Planned pricing in quantities of 1000 is $60 per unit.

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