Product category: Stand-Alone Instruments
News Release from: Tektronix | Subject: TCS101 SPI-3 and SPI-4.2 software support package
Edited by the Electronicstalk Editorial Team on 15 January 2003
Software boosts analysers
for 10Gbit/s systems
Tektronix is to provide comprehensive support for the development of next-generation network equipment operating at speeds of 10Gbit/s and beyond
The demand for faster Internet-based services is driving network equipment designers to develop new switch and router port cards that support multiservice data traffic at significantly increased bandwidths. To accomplish this, developers are using new technologies, such as System Packet Interface (SPI), to optimise data flow within a system.
This article was originally published on Electronicstalk on 15 January 2003 at 8.00am (UK)
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Implementing these technologies requires a high-performance probing, timing and characterisation solution that offers full system visibility and correlation of microprocessor, internal system bus, and external serial bus activities.
The Tektronix TCS101 SPI-3 and SPI-4.2 software support package for the TLA family of logic analysers delivers a comprehensive system-level design and debug tool for developers utilising SPI-3 and/or SPI-4.2 buses in their system designs.
"We are seeing a 'design convergence' in the development of digital systems.
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Internal and external buses, hardware and software, analogue and digital - they are no longer discrete", said David Bennett, General Manager, Logic Analyser Product Line, Tektronix: "Developers need a test toolset that can not only keep up with todayûs speeds, but accurately show the entire realm of activity between these domains.
The integration of our world-class logic analysers, oscilloscopes and bus-specific support packages offers a sound blueprint for testing and validating gigabit technologies, such as SPI-4.2."
Supporting 2.5 and 10Gbit/s rates, SPI-3 and SPI-4.2 point-to-point interfaces provide a robust and efficient means to connect a variety of physical layer devices to datalink layer devices using a single bus.
With the benefits of these new buses, however, come complex system-level debug challenges.
These include gaining access to signals with minimal effect on signal integrity; laying out test connectors in limited development board space; real-time triggering on data errors, protocol violations and other anomalies; and correlation of events on microprocessor, internal system bus and external serial bus ports.
TCS101 offers analogue and digital timing and clocking support utilising a listing window display, as well as a channel naming capability for designers of SPI-3- and SPI-4.2-based technologies.
Using TCS101 in conjunction with a TLA700 Series logic analyser, TLA7Axx logic analyser module, P68x0 connectorless probe and high-performance oscilloscope with TDSJIT3 jitter analysis software, designers have complete real-time system visibility with full correlation and optimum signal integrity.
These capabilities enable the rapid development of highly functional, scalable, standards-based networks that operate at speeds of 10Gbit/s and beyond.
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