Half-price licence for verification bundle: News from TransEDA

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The Emulation Edge verification suite can offer IC designers using hardware-assisted verification platforms faster time-to-market at half the price. Developed by TransEDA, the Emulation Edge suite enhances existing emulation environments and verification flows to dramatically speed the functional verification process while enabling more efficient use of valuable emulation resources. The suite offers a configurable HDL checker, coverage analysis for simulators and emulators, and test suite analysis in one bundle with a common interface.

At up to 50% off the regular list price for the combined set of tools, designers can speed time-to-market while keeping tool costs and vendor count to the absolute minimum.

"The Emulation Edge suite enables chip development teams to get the most out of their valuable emulation resources, while improving time-to-market by providing visibility into the verification process", said Tom Borgstrom, vice president of marketing at TransEDA.

"The suite is painless to install, integrate, learn and use so designers can get up and running quickly.

Add to this the time saved by working with a single vendor for a variety of verification tools, and designers really get an edge".

The Emulation Edge verification suite offers a powerful combination of four best-in-class verification tools that work seamlessly together and are easily integrated.

With built-in rule sets and easily configured rules, the VN-Check configurable HDL checker identifies bugs or nonsynthesisable constructs before emulation when it is easiest to fix them.

The leading Verilog, VHDL and dual-language coverage solution, VN-Cover enables designers to identify and focus test development effort on the areas of a design that have yet to be fully simulated, slashing the number of simulation iterations required.

VN-Cover Emulator enables emulator users to gain visibility into the effectiveness of their emulation runs and make more productive use of this valuable resource.

Results are compatible with VN-Cover, enabling simulation and emulation coverage to be combined for an accurate picture of overall verification completeness.

Working seamlessly with VN-Cover and VN-Cover Emulator coverage results, VN-Optimize analyses test sets from large regression suites and identifies the smallest set of tests that will meet verification goals, dramatically reducing the time and resource requirements for regression testing.

The tools in the Emulation Edge suite are part of TransEDA's Verification Navigator integrated design verification environment.

Verification Navigator provides tools that enable IC designers to manage the verification process and shorten verification time.

In addition to VN-Check, VN-Cover, VN-Cover Emulator and VN-Optimize, Verification Navigator includes VN-Control Application Specific Test Automation and VN-Property DX Dynamic Property Checking.

Verification Navigator supports all leading Verilog, VHDL and dual-language simulators; hardware assisted verification platforms from Axis Systems, Cadence Design Systems and Mentor Graphics; and is available on the Solaris, HPUX, AIX, Linux, Windows NT and Windows 2000 platforms.

The Emulation Edge verification suite, featuring VN-Check, VN-Cover, VN-Cover Emulator and VN-Optimize, is available until 31st December 2002.

Pricing starts at US $50,000 for an annual subscription licence, a 50% savings off list price for the combined tools.

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