IC Validator reduces physical verification time

Synopsys has announced the IC Validator DRC/LVS solution for in-design physical verification and signoff for advanced designs at 45nm and below.

IC Validator has been developed to deliver the accuracy necessary for leading-edge process nodes, and features scalability for efficient utilisation of available hardware.

It can reduce total physical verification time through in-design verification, stream-out reduction, incremental processing, automatic error detection and fixing, and near-linear scalability across multiple CPU cores.

IC Validator is production-ready, having been included by TSMC for the company's EDA qualification programme of design rule checking/layout verification signoff (DRC/LVS) starting from 28nm.

Prevailing approaches to physical design can be described as 'implement-then-verify', and result in multiple iterations between design and signoff.

At leading-edge nodes like 45nm and below, the implement-then-verify approach can be slow and may complicate convergence as layout corrections can alter design objectives such as area, timing, and power.

In-design physical verification brings the full physical verification constraints into the design phase, helping to ensure clean layout upon leaving the design environment and avoiding late-stage surprises close to tape-out.

With in-design verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time.

In addition, IC Validator can automatically discover and fix design rule violations within the global context of the design.

Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure.

Working in concert with IC Compiler, IC Validator's in-design flow reduces such iterations by performing signoff-quality, timing-driven metal fill during the design phase.

Back to top