Reference design flow eases chip evaluation

Synopsys' Design Compiler Ultra topographical synthesis engine enables engineers to accurately predict chip performance results during logic synthesis.

Synopsys and UMC have released a 65nm hierarchical, multivoltage RTL-to-GDSII reference design flow.

The flow is based on Synopsys' Galaxy Design Platform and features the IC Compiler place-and-route solution and the Design Compiler Ultra topographical synthesis solution for comprehensive design implementation support.

Key features of the reference flow include support for power management with multivoltage design and power gating, as well as design-for-manufacturing (DFM) capabilities with the addition of critical area analysis (CAA).

Power gating reduces standby leakage by shutting off areas of the chip that are not in use.

The CAA capability, provided in IC Compiler, determines the likelihood of random particle defects affecting the overall design.

Engineers can use this capability to identify design structures that have a higher probability of yield loss and correct them before manufacturing.

This combination of tools and flow better equips engineers to reduce power consumption and improve yield, both significant 65nm design challenges.

The reference flow also uses Synopsys' Design Compiler Ultra topographical synthesis engine, enabling engineers to accurately predict chip performance results such as timing, area, testability and power consumption during logic synthesis.

Using this engine, engineers can evaluate the chip and make early-stage modifications to provide a better starting point for physical implementation, reduce or even eliminate iterations between synthesis and physical implementation and accelerate the design cycle.

"Our goal is to help customers increase their ability to achieve first-pass silicon success", said Stephen Fu, Deputy Director of the IP and Design Support Division at UMC.

"Our ongoing collaboration with Synopsys has helped us develop this validated 65nm reference flow and we expect this will help reduce design risk, lower power consumption and reduce turnaround time for our customers".

The reference flow also includes automatic level shifter insertion, placement, optimisation and verification.

Voltage area (VA) creation, power-switch cell insertion, VA-aware physical optimisation, clock-tree synthesis and routing are used to reduce dynamic power consumption.

The multivoltage timing flow closure includes signal integrity (SI) prevention, repair and signoff and multivoltage analysis.

Additional DFM features include redundant via insertion, via-farm/via-array rules and timing-driven metal fill.

Synopsys Professional Services and UMC engineers validated the reference flow using the test chip tape-out for "Leon", an open-source 32bit RISC microprocessor core.

The test chip was partitioned into multiple voltage regions using the low-power reference flow.

UMC also used its own internally developed library for its 65nm design process.

The resulting test chip is highly configurable and expandable with additional digital and analogue/mixed-signal intellectual property.

"As technology nodes become more complex, our strategic partnerships with world-class foundries like UMC are vital to help customers solve power management and yield challenges", said Rich Goldman, Vice President of Strategic Market Development at Synopsys.

"Through our collaboration with UMC, we now have a validated 65nm reference flow that helps engineers to meet their design schedules and incorporates manufacturing technology for improved yield".

The reference flow is derived from Synopsys' Pilot Design Environment and was developed by UMC and Synopsys Professional Services.

The reference flow uses Synopsys' Galaxy Design Platform, including the Design Compiler Ultra synthesis solution, IC Compiler place-and-route solution, DFT MAX test solution, JupiterXT floorplanning solution, PrimeRail rail analysis solution, PrimeTime sign-off solution, Star-RCXT extraction solution, Hercules PVS physical verification solution and TetraMAX automatic test pattern generation (ATPG) solution.

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