Test module suits design companies

TetraMAX failure diagnostics data is exported to the new Odyssey DFT module to facilitate comprehensive failure analysis and rapid yield improvement of fabricated devices.

Synopsys has released the Odyssey Design for Test (DFT) module for use by design organisations.

The Odyssey yield management software has been widely adopted by leading semiconductor manufacturers to correlate and analyse diverse datasets needed for product yield enhancement.

The TetraMAX automatic test pattern generation (ATPG) solution creates manufacturing tests and identifies logic in a design that could contribute to observed tester failures.

TetraMAX failure diagnostics data is exported to the new Odyssey DFT module to facilitate comprehensive failure analysis and rapid yield improvement of fabricated devices.

Fabless firms have adopted the Synopsys solution because shorter yield learning cycles can increase net profits over a product's life cycle.

"If a device fails production test, we want to understand why", said Bruce Cory, DFT Manager at Nvidia.

"The Synopsys yield management solution allows us to leverage design, fabrication and production test data to analyse TetraMAX diagnostic isolations across multiple die and wafers".

"The software helps identify underlying failure signatures to enable faster yield ramp".

Semiconductor foundries typically supply their fabless clients with parametric data associated with the manufacture and testing of production parts, but until now there was little designers could do with the information to improve product yield.

With the Synopsys tools in hand, designers are now leveraging the foundry-supplied data together with failure diagnostics accumulated from production runs to help determine the root cause of yield loss.

Designers at Nvidia and TranSwitch are using the Odyssey solution to correlate circuit failure candidates reported by TetraMAX diagnostics with foundry-supplied information.

Data mining and cross-correlation features in Odyssey assist designers in quickly determining both the impact of measured process parameters on product yield and whether failing parts are caused by systematic or random processes.

"Nanometer manufacturing steps can distort device and wire geometries, leading to more frequent failures at process corners", said Zahi Abuhamdeh, director of DFT and diagnostics at TranSwitch.

"Also, the foundry's occasional tweaking of the process can cause subtle corner failures that previously did not occur".

"The Synopsys yield enhancement solution has provided us the ability to determine whether failing parts from a product run are due to foundry, specification, or design specific issues".

"In the latter scenario, making alterations to a single library cell or including or removing a foundry recommended design rule might lead to a step increase in the product's yield".

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