Product category: Design and Development Software
News Release from: Synopsys | Subject: Design Compiler 2007
Edited by the Electronicstalk Editorial Team on 23 April 2007
Design synthesis takes topographical
route
Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle.
The latest release of the Synopsys Design Compiler synthesis solution extends topographical technology to accelerate design closure for designs using advanced low power and test techniques, boosting designer productivity and IC performance Topographical technology allows designers to accurately estimate a chip's power consumption during synthesis and address any power issues early in the design cycle
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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