Product category: Design and Development Software
News Release from: Synopsys | Subject: Composite Current Source (CCS) models
Edited by the Electronicstalk Editorial Team on 02 April 2007
Timing and noise models work with Galaxy
platform
Two design software companies team up to include high-accuracy CCS timing and noise models in the Galaxy design platform
Synopsys and Virage Logic have announced support of Composite Current Source (CCS) models for all advanced process-node versions of Virage Logic's Self Test and Repair (STAR) Memory, Area, Speed and Power (ASAP) Memory and ASAP Logic Standard Cell product lines Used in conjunction with the Synopsys Galaxy Design Platform, the high-accuracy CCS timing and noise models allow the designer to reduce guard-band margins during design implementation and sign-off, thus improving design performance and reducing design iterations
This article was originally published on Electronicstalk on 9 Apr 2007 at 8.00am (UK)