Product category: Intellectual Property Cores
News Release from: Synopsys | Subject: DesignWare Mixed-Signal connectivity
Edited by the Electronicstalk Editorial Team on 13 July 2006
IBM and Chartered team with Synopsys
Synopsys USB, PCIe, SATA and XAUI PHYs for high-volume, low-power applications available for foundries' leading-edge processes
Synopsys, a world leader in semiconductor design software, has announced that IBM and Chartered Semiconductor Manufacturing have agreed to support Synopsys' DesignWare Mixed-Signal connectivity intellectual property (IP) on the 65 nm process developed for Common Platform technology As part of this agreement, Synopsys is porting PHYs for USB 2.0, PCI Express (PCIe), SATA and XAUI protocols to the 65 nm process technology developed by Chartered, IBM, Infineon Technologies and Samsung, and also porting the DesignWare USB 2.0 nanoPHY IP to IBM and Chartered's 90 nm process node
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)
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