Leading experts in embedded software development
Click on the advert above to visit the company web site

Product category: Intellectual Property Cores
News Release from: Synopsys | Subject: DesignWare USB 2.0 nanoPHY
Edited by the Electronicstalk Editorial Team on 7 February 2006

Interface IP eases USB 2.0 integration

Register for the FREE Electronicstalk email newsletter now! News about Intellectual Property Cores and more every issue. Click here for details.

New USB 2.0 PHY IP is tailored specifically for low power consumption, small area and high yield

Synopsys has added the new DesignWare USB 2.0 nanoPHY IP to its existing DesignWare USB 2.0 physical layer (PHY) product line. The new mixed-signal PHY IP builds on Synopsys' three years of leadership in successfully providing USB 2.0 PHY intellectual property (IP) in more than two dozen process node and configuration combinations.

The new DesignWare USB 2.0 nanoPHY IP is tailored specifically for low power consumption, small area and high yield.

It targets designers of mobile, high-volume consumer applications such as next generation handheld game machines, feature-rich smart phones, digital cameras, and portable audio and video players.

Over the last three to four years, designers have successfully integrated the USB 2.0 bus interface into many systems-on-chip (SoC) designs.

The initial applications started with PCs and then moved into peripherals such as printers, scanners, and external hard drives that were typically plugged into a power source.

However, as the bus standard has become more pervasive, it has been quickly adopted into a wide range of battery powered consumer applications that are more cost sensitive and require very low power.

'This new DesignWare USB 2.0 nanoPHY IP follows many years of success with our volume-proven USB PHY IP solution', said Guri Stark, Vice President of Marketing, Solutions Group at Synopsys.

'Our experience with leading semiconductor companies has enabled us to continuously innovate and address our customers' needs for low-power cost-competitive IP that helps deliver high yield, reduced area and increased interoperability'.

'As part of our complete USB IP solution, we expect the new PHY IP to be adopted in many cost- and power-sensitive designs for the competitive mobile and consumer market'.

The new DesignWare USB 2.0 USB nanoPHY IP is expected to be available in Q1 of calendar 2006.

Synopsys: contact details and other news
Email this article to a colleague
Register for the free Electronicstalk email newsletter
NEW
Electronicstalk Home Page

Related Business News

Cast Selects Avery Design Systems For...
...Pci Express Verification Ip. Semiconductor intellectual property provider CAST, Inc. today announced that it has begun using the PCI-Xactor test environment from Avery Design Systems to verify its current and future PCI Express IP cores.

Vsia Announces Release Of Qip Metric...
...Now Publicly Available With Hard Ip Extension. The VSI Alliance , the leading IP standards body for the electronics industry, today announced the Quality IP Metric version 3.0, which includes the hard IP extension, is now publicly available.

Gda Technologies Selected By Renesas Technology...
...For Pci Express To Amba Axi Bridge. Gda Technologies, Inc., a fast growing supplier of Intellectual Property and Electronic Design Services , today announced that Renesas Technology Corp., a leading semiconductor company, has selected GDA for development of a PCIE 2 AMBA AXI Bridge to be

Altera delivers first FPGA-Based IP support for Ethernet protocols
Bangalore, India: Altera Corp. has announced FPGA-based support for Ethernet communications protocols used in industrial automation applications, including ProfiNet, Ethernet/IP, Modbus-IDA, EtherCAT, SERCOS III Interface, and Ethernet Powerlink.

Ieee Picks Up Vsia's Standards Work
The IEEE has formed two study groups to explore the creation of IEEE standards based on work done at the VSI Alliance.

Search the Pro-Talk network of sites

Leading experts in embedded software development