Product category: Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial Team on 23 October 2001
IBM takes in Synopsys design planner
The Synopsys Chip Architect design planner has been integrated into IBM's Blue Logic design methodology
The design kit will provide IBM's customers a new hierarchical top-down design flow which allows chip designers to accurately account for physical effects much earlier in the design flow. The result is increased predictability of chip performance and faster time to market on multi-million-gate designs, implemented using a hierarchical approach.
This article was originally published on Electronicstalk on 23 October 2001 at 8.00am (UK)
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Customers using IBM's advanced silicon technologies can now leverage the benefits of Chip Architect, Physical Compiler, and IBM tools to design multi-million-gate designs.
Design kits supporting Chip Architect and Physical Compiler are now available for Cu-11, SA-27E, SA-12E, and SA-12 technologies.
"We have established a design flow around Synopsys' Physical Synthesis solution, applied the flow to real customer designs, and experienced an improvement in timing convergence and correlation with IBM back-end tools", said Dave Balkin, director of ASIC development at IBM.
"Combining Synopsys' Physical Synthesis technology with IBM's advanced ASIC technology enhances our ability to meet our customer's changing requirements".
"Our copper technologies are capable of supporting designs of up to 40 million gates.
In order to achieve their goals of high performance and rapid time to market, many of our customers are requesting support for a hierarchical implementation flow.
The addition of Chip Architect to our design flow will help our customers using Physical Compiler to achieve faster timing closure by providing them with an efficient means to partition and floorplan their designs into blocks, then work on parallel block implementations with excellent correlation to final synthesis and placement", said Balkin.
"IBM is a leading supplier of the state of the art ASICs worldwide.
We are very pleased with the progress of our on going partnership.
Our mutual customers have taped out numerous chips with Physical Compiler in IBM's Blue Logic flow", said Sanjiv Kaul, senior vice president and general manager, Physical Synthesis Business Unit, Synopsys.
"With the introduction of Chip Architect into the IBM flow, our customers can now design even bigger and faster chips with improved predictability.
IBM's support is indicative of the value Chip Architect adds to the current hierarchical flows".
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