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Product category: Design and Development Software
News Release from: Synopsys | Subject: NEC Electronics (Europe)
Edited by the Electronicstalk Editorial Team on 10 October 2001
Physical design planner aids telecomms
ASIC design
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NEC Electronics (Europe) has successfully used Synopsys' Chip Architect physical design planner to tape out a 3.8 million gate, 622MHz telecommunications ASIC chip.
NEC Electronics (Europe) has successfully used Synopsys' Chip Architect physical design planner to tape out a 3.8 million gate, 622MHz telecommunications ASIC chip, using NEC's 0.18-micron process with ball grid array packaging By adopting Chip Architect in its flow, NEC was able to substantially reduce design time by several weeks