Product category: Design and Development Software
News Release from: Synplicity | Subject: Certify 5.0
Edited by the Electronicstalk Editorial Team on 21 August 2001
Software automatically partitions FPGA
designs
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes.
Synplicity has automated its Certify verification synthesis software to speed the development of FPGA-based ASIC prototypes The software can now perform many time consuming tasks automatically, including partitioning, gated-clock conversion and pin multiplexing, shaving days or weeks off of the prototyping process
This article was originally published on Electronicstalk on 16 Apr 2008 at 8.00am (UK)
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Featuring Synplicity's new Quick Partitioning Technology, the Certify software now provides designers with the capability to automatically partition an ASIC design onto multi-FPGA custom boards for the development of ASIC prototypes.