Multicore processor optimised for network services

Cavium Networks has introduced the industry's first single-chip network services processor (NSP) family for secure, Layer 3 to Layer 7 networking applications.

Cavium Networks has introduced the industry's first single-chip network services processor (NSP) family for secure, Layer 3 to Layer 7 networking applications.

Today's implementations of higher layer application processing require a myriad of chips including control plane processors, data-plane processors and coprocessors for Internet services and security.

Cavium's new Octeon NSPs feature a revolutionary new SoC architecture that integrates the functionality of the multiple processor types to deliver up to 5x benefit in price, performance and power over existing solutions for Internet services, content and security processing in networking applications.

The cnMIPS core is Cavium's implementation of the MIPS64.

Octeon processors include up to 16 of these cnMIPS cores, with Release2 enhancements and additional built-in hardware acceleration for content and security processing, together with on-chip coprocessor blocks for Internet services acceleration and multiple Gigabit Ethernet, SPI-4.2 and PCI-X interfaces.

Octeon NSPs provide full compatibility with the large base of developed application software and development tools available for the industry standard MIPS instruction set architecture (ISA) licensed from MIPS Technologies.

The next phase in the evolution of the Internet is the deployment of application-aware networks upon which secure, co