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Sequence Design is to host a low-power design seminar in Tokyo on Friday 4th July from 1300 to 1630.
The event is cosponsored by Sun Microsystems.
Presentations will focus on methodologies to analyse and optimise power at the RTL level, along with a demonstration of Sequence's PowerTheater tool suite.
In addition, an overview of techniques to reduce soc leakage power and voltage drop will be discussed.
Sequence has held more than 10 seminars dedicated to low-power design methodology since it launched its NanoCool initiative about a year ago.
Sequence is honoured to have guest speakers from Toshiba and Ricoh presenting results of their own low-power design efforts, and the seminar will conclude with an executive briefing detailing future challenges in this area, and the types of EDA tools being designed to deal with them.
"There is little doubt that design success in this decade will be tied directly to a company's ability to manage power consumption effectively", according to Vic Kulkarni, Sequence President and CEO.
"With its deep consumer electronics and portable computing experience, Japan is positioned to play a leadership role in this new era of "power-aware" design".
The seminar will take place at the World Trade Centre Building 38F "Sky Hall", Tokyo, Japan.
 

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