Product category: Intellectual Property Cores
News Release from: Silicon Hive | Subject: HiveFlex VSP2100 Series
Edited by the Electronicstalk Editorial Team on 11 October 2006
Cores boost video signal processing
HiveFlex VSP2100 Series of processor cores targets HD widescreen TVs with high quality video displays
Silicon Hive announced the HiveFlex VSP2100 Series of processor cores for video signal processing applications at the Micro Processor Forum's 25th anniversary event in San Jose, with a licensing programme starting by the end of this year. The HiveFlex VSP2100 Series targets HD widescreen TVs with high quality video displays.
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The HiveFlex VSP 2100 series is built on a tiled architecture with one tile offering 112GOPS of 16bit equivalent integer performance at 200MHz, in a footprint of about 4mm2 in a typical 65nm process.
A tile is fully programmable and can support various video processing algorithms, including, codecs, de-interlacing, picture rate up-conversion, spatial scaling etc, for displays up to HD (1920 x 1080) resolution.
An entire video pipeline can be implemented with repeated use of the hardware tiles with different software running on each tile.
TV and SoC manufacturers can now bring their products to market quickly, with the possibility of incorporating either, their own or even 3rd party algorithms in software.
The HiveFlex VSP2100 series of processor cores are delivered as synthesisable soft IP with a complete I/O subsystem for easy integration, and a full suite of test and verification tools.
Further reading
Agere signs for comms processor IP
Agere Systems has signed a new licence agreement for Silicon Hive's HiveFlex CSP 2000 Series application specific communications processors
Imaging sensor takes processor onbaord
MagnaChip has integrated the HiveFlex ISP 2200 processor into a new imaging sensor, the MC531EA
Alliance to create video signal processing demo
Silicon Hive and AllGo Embedded Systems have signed an agreement to codevelop a video signal processing demonstration system
In addition the company sells the HiveGates VSP2100 Series FPGA based real time hardware emulation system for quick prototyping exercises.
Ease of use has been maintained as with other HiveFlex processors by maintaining C programmability via Silicon Hive's HiveCC compiler technology.
Geoff Burns, Silicon Hive's Vice President of Product Management said: 'Time is ripe for domain specific programmable solutions for high-performance video processing'.
'The HiveFlex VSP2100 series caters to different market segments (mobile to HDTV)'.
'Not just video post processing for displays but also coding and decoding (H.264)'.
'This enables our customers to use one solution for the entire video pipeline which brings down SoC design time dramatically'.
The HiveFlex VSP2100 series is built on a tiled architecture with each tile containing separate applications and vector compute engines and a programmable DMA engine.
The compute engines perform a variety of scalar and vector operations in parallel.
Each tile supports two levels of memory hierarchy level-1 (L1) and level-0 (L0).
Video data planes, i.e regions and windows of pixels, are stored in L1 and L0 memories.
Because they support multiple video planes, L1 and L0 memories are content-aware.
This hierarchical approach reduces the external memory access bandwidth requirements by up to a factor of 20 over traditional designs.
Customers have the flexibility to choose several types of design time parameters, among others: the size of video region and window of interest per video plane; the number of issue slots; choice of vector instructions and functional units per issue slot; SIMD-factor (vector widths ranging from 4 to 128 ways); the number of bits per vector element (from 8 to 32); the number of words used in L0, L1, program, scalar, and vector memories; and the sizes of distributed register files
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