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The latest version of Summit Design's Visual Elite graphical based ESL design product includes Advanced SystemC modelling and analysis capabilities.
Rami Rachamin, Summit's Director of Marketing, says previous versions of Visual Elite supported SystemC design built on the HDL engine.
The latest version of the tool, version 4.0, includes native SystemC constructs that allow users to model and verify designs in SystemC.
"This is the first version of Visual Elite that fully understands the concept of system-level design in its graphical entry, design and verification", says Rachamin.
The HDL version of the tool helped gate-level designers learn to design with Verilog and VHDL.
Rachamin says the new version of Visual Elite helps get hardware designers and even C/C++ coders up to speed on creating systems using the SystemC language.
Version 4.0 of Visual Elite allows users to create systems with prebuilt graphical blocks and create their own text blocks as they become more familiar with the language.
Rachamin says the tool also offers "viewing duality", giving users a hardware-centric view of the design structure (module hierarchy and interfaces), side by side with a C/C++ view on the language structure.
The tool features a browser that gives users a view of the dependencies of both hardware and software design constructs.
Rachamin says this is useful when coding C/C++ and helps with identifying problems.
The view browsers, along with the text editor, are synchronised and active during modelling and simulation, providing insight into design structure and execution.
Visual 4.0 also has new transaction-level verification features, including a transaction view in waveform, hierarchical channels and interface method calls.
It also includes thread-switching monitors, which allow users to switch and monitor all threads in the waiting queue.
And it includes "stack visualisation" and "watch" windows, as well as "on text" object value feedbacks.
The tool also allows users to perform debugging during design elaboration.
Visual Elite also supports graphical state machines and mapping of SystemC RTL to VHDL using Summit's FastC speedy SystemC simulator, allowing users to employ SystemC for actual design, not just modelling.
The high-end System Architect package offers support for the visualisation of "tokens distribution" in the graphical waveform (data flow diagram) and offers a new set of generic models for bus, processors as well as a PCIbus and IEEE1394 performance models.
The System Architect package offers a set of functions and classes written on top of SystemC that can be instrumented into SystemC functional code and trace and log "tokens" of data.
Data can be analysed and statistically analysed allowing users to quickly discern relevant performance statistics such as latency, bandwidth and resource use.
In addition, the company announced that the tool supports and links up to ISS models from MIPS and Denali.
Summit's Visual ESC package integrates the MIPSsim ISS and is compatible with the MIPS Software Toolkit, which includes the MIPS SDE software tool chain for the 5K processor family.
Summit has also integrated Denali's MMAV and PureSpec verification IP platforms with its Visual ESC for external memory interfaces and PCI Express designs.
Visual Elite 4.0 starts at $15,000 and is available for beta release.
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