Product category: Memory Devices and Modules
News Release from: Renesas Technology Europe | Subject: AG-AND Flash memory
Edited by the Electronicstalk Editorial Team on 15 December 2003

Novel cell technology
shrinks Flash die size

Hitachi and Renesas Technology have developed a basic Flash memory cell technology that achieves the world's smallest cell area of 0.016um2 and fastest programming speed of 10Mbyte/s

Hitachi and Renesas Technology have developed a basic Flash memory cell technology that achieves the world's smallest cell area of 0.016um2 (on a 1bit basis) and fastest programming speed of 10Mbyte/s. This basic memory cell technology improves the source-drain structure of an AG-AND (assist gate-AND) Flash memory cell featuring multilevel cell technology and high speed, enabling the memory cell area to be reduced by approximately 30% when using a 90nm process.

Renesas Technology plans commercial production of 4Gbit AG-AND Flash memory based on this technology in the third quarter of 2004, and will offer compact, high-density, high-speed recording media for the "ubiquitous computing society".

High-density Flash memory is beginning to permeate our lives as a bridge medium (information delivery device), especially in mobile applications, including use as image storage memory for digital cameras and mobile phones, and USB storage as replacements for floppy disk drives.

Next-generation Flash memory cards offering portability of large-volume, high-quality moving picture data such as movies will require significantly high density and higher programming speeds to handle fast data downloads.

In response to these needs, in 2001 Hitachi and Renesas Technology jointly developed a first-generation AG-AND Flash memory offering a high programming speed of 10Mbyte/s through the use of assist gates (AGs) to prevent intercell interference together with multilevel cell technology.

Renesas Technology currently mass-produces 130nm process 1Gbit AG-AND Flash memory.

However, to meet the need for high density while maintaining high speed operation, it became necessary to make advances in memory cell structure to restrict lateral expansion by altering the source-drain structure, and minimise the memory cell area as far as physical limitations allow.

Against this backdrop, Hitachi's Central Research Laboratory and Renesas Technology collaborated in the development of a basic technology for second-generation AG-AND Flash memory that offers both high-speed writing and a fine process.

The features of this newly developed technology are summarised below.

The source and drain of a memory cell transistor are formed as an inversion layer that appears in the silicon substrate when a voltage is applied to the AG, instead of the conventional diffusion layer.

As the inversion layer is formed only in the extremely shallow region of the substrate just beneath the AG, there is no lateral spread.

As a result, it has become possible to reduce the memory cell area from the previous 6F2 (where F is the feature size) to the physical limit of 4F2.

Through combination with multilevel cell technology, the area per bit has become 2F2, and the world's smallest memory cell has been achieved, at 0.016um2 for a 4Gbit device using a 90nm process.

This represents an approximately 30% decrease compared with previous 130nm process first-generation memory cells, enabling high-density Flash memory cards to be realised.

High-speed memory cell programming at a low voltage has been made possible by the hot electron injection method used with the 1Gbit product.

In developing the 4Gbit product, a maximum programming speed of 10Mbyte/s has been achieved even with the use of multilevel technology.

This new technology makes possible fast downloading and portability of large volume content data such as moving pictures and music.

As a result, usage scenarios previously restricted to digital cameras and PCs can now be extended to mobile terminals and digital home appliances, expanding the range of system solutions that employ Flash memory as a storage medium.

These results were announced at the 2003 IEEE International Electron Devices Meeting (IEDM) last week in Washington, DC.

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