News Release from: Real Intent
Edited by the Electronicstalk Editorial Team on 28 February 2006

Clock tool software adds debug and simulation

Clock Intent Verification automatically detects clock crossings and insures that the proper synchronisers are present in the design.

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Real Intent has significantly extended the capabilities of its industry's leading clock tool, Clock Intent Verification. These capabilities include vastly improved design navigation and debug, as well as add an option linking the best of static and dynamic verification, Clock Intent Verification SimPortal to Real Intent's Verix product line. With the convergence of technologies onto a single die, SoC designs invariably include multiple islands of logic driven by different clock domains.

One of the challenges of SoC design is insuring that the proper structures are present between these clock domains to synchronise the data transfers between domains.

Existing simulation-based dynamic verification solutions can not verify the correctness of these structures because functional simulation does not model the effects of metastability.

Clock Intent Verification automatically detects clock crossings and insures that the proper synchronisers are present in the design.

Clock Intent Verification has been extended to more tightly integrate the leading Novas Verdi debugging software.

Unique advantages of the new integration include clock domain colouration, which is supported in text and graphical views throughout.

Startup and runtime performance, especially for large designs has been increased up to 10x with its newly designed integration architecture.

'In our large multi-clock- domain designs, perfecting the transfer of data across clock domains is critical to insure consistently correct operation', said TR Ramesh, Director of VLSI Engineering at Ikanos Communications.

'Without a clock domain crossing tool, insuring the correctness of this part of the design would have been difficult, time-consuming and risky'.

'With excellent local support we were able to get productive use of Verix Clock Intent Verification in a short time'.

Even when the proper structures are present, the functional behaviour of signals can have impact on reliability of clocking.

In this area, simulation can help.

Clock Intent Verification SimPortal is an option that allows users to run their sign-off vectors on their design, with the effects of metastability simulated.

Design source files require no modification, and side files are generated which contain the metastability logic.

After running the dynamic simulation with these side files, designers can have complete confidence that their design has all clocking issues covered.

'Making metastability simulation available in a fully automated way makes Clock Intent Verification SimPortal uniquely popular with our users'.

'It links the best of static and dynamic verification in a way that easily fits user flows'.

'We have detected clocking issues that can be missed during static clock analysis and debug, providing a complete and reliable solution for our customers', remarked Prakash Narain, President and CEO of Real Intent, The Verix family uses the power of formal analysis to detect bugs that are hard to find.

Verix can detect defects entirely missed with other RTL verification techniques.

The Verix Convergence Engine improves the capacity and performance of the entire Verix product family - Implied Intent Verification, Expressed Intent Verification and Clock Intent Verification software - so that many designs which were impossible to formally verify, can now be verified.

PureTime, a software timing exception verifier, extends Real Intent's formal technology to address design implementation challenges early in the design cycle.

It can prove the correctness of timing exceptions created by designers, or in existing intellectual property (IP), using exhaustive analysis and help avoid timing exception errors that create schedule delays, chip re-spins or failing hardware.

The new release of Clock Intent Verification and the new Clock Intent Verification SimPortal option are available now.

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