News Release from: Real Intent
Edited by the Electronicstalk Editorial Team on 10 April 2003
More scope for assertion-based formal verification
Real Intent has released the latest version of its flagship product - Verix 4.0 - that delivers a multi-million-gate capacity for formal assertion verification.
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Real Intent has released the latest version of its flagship product - Verix 4.0 - that delivers a multi-million-gate capacity for formal assertion verification. Armed with new checks, more capacity and performance and a push-button automation, Verix is now deployed by several customers on very large, complex designs. Verix, first introduced in 2000, is Real Intent's pioneering assertion-driven formal verification system for exhaustively verifying that a design is free from a large class of errors.
It includes over 14 classes of automatic assertions, as well as a Verilog/VHDL like assertion language that allows users to define their own design assertions with minimal learning curve.
With a greatly enhanced pushbutton automatic hierarchical design processing, Verix 4.0 can now process any top-level multi-million-gate design without any user partitioning.
The hierarchical formal methodology built into Verix automatically combines the formal results of lower blocks to formally verify higher blocks.
By leveraging this scalable and hierarchical methodology, designers can now formally verify multi-million-gate designs and enjoy a much larger capacity than other formal verification products.
The Verix 4.0 proof engine has gone through a major performance upgrade and it can now prove assertions 10-20x more complex than the previous versions.
The new proof radius of Verix covers significantly more design assertions than before.
For FSM checking, Verix 4.0 extracts all the state machines in the given RTL and then applies a set of powerful assertion checks to validate the correct operation of these FSMs.
Verix checking ensures that all states can be reached, the FSM has no single-state or pair-wise state deadlock and that none of the state vector bits are stuck.
These assertions are automatically created by Verix from the RTL.
Newly enhanced clock intent verification capability in Verix 4.0 applies even more rules to verify the stability and correctness of data transfer between clock domains.
It automatically identifies all the asynchronous clock domains and the hazards for signals crossing those domains.
Verix detects many types of design errors such as absence of several types of synchronisers, glitch potentials, flop resets from asynchronous domains and many other design bugs that violate safe domain crossing principles.
It further suggests appropriate formal assertions to exhaustively verify the logical correctness of safe data transfer.
All the user needs to supply is the RTL and the top-level clocks.
Verix 4.0 now supports Accellera Standard OVL assertions.
Users can now apply formal analysis to verify behaviours expressed in OVL.
Users can plug-and-play OVL assertions between Verix and simulations to do formal and dynamic analysis.
Verix will be shown on the show floor at Real Intent's booth at the Design Automation Conference in Anaheim, California in June 2003.
Verix 4.0 starts at US $60,000, and is available now for Sun, HP and Linux platforms with support for Verilog and VHDL designs.
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Copyright © 2000-2006 Pro-Talk Ltd, UK. Based on news supplied by Real Intent - Subject: Verix 4.0