News Release from: Ponté Solutions
Edited by the Electronicstalk Editorial Team on 19 April 2005

New company addresses design for yield

Ponte Solutions has revealed plans to deliver the semiconductor industry's first full-chip, model-based design-for-yield solution.

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Ponte Solutions has revealed plans to deliver the semiconductor industry's first full-chip, model-based design-for-yield solution. Ponte (formerly known as E-Z-CAD) has developed unique technology that will enable design teams to enhance integrated circuit (IC) yields prior to design tapeout, before committing chips to multi-million-dollar silicon manufacturing runs. Ponte's technology aims to bridge the 'yield gap' between design and manufacturing, dramatically reducing the cost and time to volume of ICs for fabless semiconductor companies, foundry service suppliers and integrated device manufacturers (IDMs).

Ponte is unveiling three core capabilities that form the foundation of its design for yield solution: a comprehensive unified yield modelling platform, high-capacity data processing, and robust yield analysis.

Combined, these capabilities can enable design teams to analyse and predict yield characteristics of multi-million-gate, sub-100nm ICs, while protecting the intellectual property of semiconductor manufacturers.

'The challenge of predicting and ensuring yields is one of the largest problems the semiconductor industry faces at sub-130nm process nodes', stated Jim Hogan, General Partner at Telos Venture Partners and Ponte board member.

'Ponte is a company with the outstanding yield understanding, design expertise, team and technology to solve this problem'.

'They are in the right place with the right products and technology when customers are looking for a solution to their yield issues'.

The company has received Series A funding of approximately $10 million from private individuals and leading venture capital (VC) firms such as Telos Venture Partners, US Venture Partners and Incubic.

The company is cofounded by a team of electronic design automation (EDA) and semiconductor veterans, including: Alex Alexanian, CEO, who previously led and founded Mosaic Systems - a semiconductor memory company; Ara Markosian, CTO, who held senior engineering roles at Monterey Design Systems and Aristo Technology; and Sedrak Sargisian, Vice President of Engineering, who also held senior engineering roles with Monterey Design Systems, Aristo Technology and Intel.

They are joined by Arklin Kee, Vice President of Business Development, who has led sales efforts for InTime Software, HLD Systems and Cadence Design Systems and industry veteran Nitin Deo, Senior Vice President of Marketing, Applications and Customer Support, who was formerly Vice President of Product Marketing and Vice President of Japan sales from Magma, and former Vice President of Marketing at Moscape.

With each successive process generation, optimal yield has become progressively lower.

Analysts predict that, without intervention, yields on the 65nm process node are likely to be in the single digit numbers - if the processes yield at all.

Designers and manufacturing groups have traditionally relied on design rules to convey all process information to a design flow.

However, with 130nm and smaller process nodes, this approach began to break down; two designs following the same rules may yield different results.

Lack of visibility into yield problems at the design stage has become the main problem of IC manufacturing at sub-130nm geometries.

'If you don't have good yields, you don't have a product to sell'.

'If you face yield problems at the manufacturing stage, you are late'.

'These are the realities today', stated Alex Alexanian, CEO of Ponte.

'The semiconductor industry today needs EDA tools that can provide visibility into yield problems and automatically fix these problems at the design stage, before it is too late'.

'Ponte's technology is an inevitable and effective solution for addressing yield challenges at sub-130nm geometries'.

Ponte plans to address this issue with products that will bridge the gap between design and manufacturing, offering easy data setup and integration with standard EDA flows.

Ponte's products are based on three core technologies: a comprehensive unified yield modelling platform based on statistical yield models; a high-capacity data processing platform that can process billions of nanometre structures overnight; and robust yield analysis technology that handles custom and cell-based structures to ensure accurate full-chip yield analysis.

The technology delivers design-content-specific analysis for various random and systematic defects, enables 'what-if' analysis, and is orders of magnitude faster than rule-based systems.

The company plans to deliver its first design-for-yield software products based on these technologies for broad deployment in 2005.

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