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PowerEscape Analyzer and PowerEscape Analyzer+Cache are designed to help algorithm designers, software developers and system architects create cooler, faster and cheaper electronic appliances and systems.
The products are the first commercially available tools that enable designers to optimise the critical algorithms of today's electronic appliances and systems for lower power.
The new PowerEscape products address the increasingly problematic power and performance issues in electronic systems.
More and more features are being incorporated into system chips used for consumer devices, and as a result, these devices are increasingly manipulating large amounts of data-thus performing more memory functions.
This trend holds true for a wide variety of electronic devices, from digital cameras, cellphones, and PDAs, to industrial applications such as Internet routers and cellphone network basestations.
Because memory access dominates power consumption in all such devices, PowerEscape Analyzer and PowerEscape Analyzer+Cache focus on optimising power and performance by minimising memory operations.
"Traditional dynamic power reduction techniques make reaching performance goals very difficult, if not impossible", said Guido Arnout, President and CEO of PowerEscape.
"The PowerEscape products introduce power estimation and analysis early in the design cycle, enabling designers to make decisions about power up front to meet or exceed their power goals.
In beta testing, PowerEscape Analyzer has shown power reductions of more than 80%, compared to the less than 5% power savings HDL or physical level power reduction techniques typically yield".
PowerEscape Analyzer works with any ANSI C compliant algorithm or software and produces detailed reports on memory accesses and energy consumption of the memory subsystem, pinpointing the source code that causes the most costly data transfers.
In addition, PowerEscape Analyzer records the exact source code location at which memory usage peaks, along with the data structures in memory at that time.
This information helps designers tune their source code for lower power and improved performance, while reducing overall memory requirements.
PowerEscape Analyzer+Cache works in tandem with PowerEscape Analyzer and provides simulation of L1, L2 and L3 caches in a wide variety of configurations at unprecedented speeds.
PowerEscape cache produces detailed reports on cache efficiency by source code and data structure.
This information helps designers optimise both their source code and memory subsystems, including cache size and policies, for lower power and improved efficiency.
Detailed, source-level feedback on data transport bottlenecks and cache behavior aids designers in striking the right balance between software running on a general purpose CPU, accelerated software on a DSP or custom-designed coprocessor, and dedicated hardware.
PowerEscape Analyzer and PowerEscape Analyzer+Cache easily fit into existing gcc-based algorithm development flows, integrating effortlessly into a makefile-based build system.
PowerEscape Analyzer is based on technology originally developed at IMEC, Europe's largest independent microelectronics and nanotechnology research centre.
PowerEscape Analyzer and PowerEscape Analyzer+Cache are available immediately.
One-year, single-user subscription pricing starts at $10,000 for PowerEscape Analyzer or $25,000 for PowerEscape Analyzer+Cache.
The products run on Red Hat Enterprise Linux, Fedora Core from the Red Hat sponsored Fedora Project, Sun Solaris, Microsoft Windows using Cygwin, and Apple Mac OS X.
They require gcc 2.95 or higher.
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