Product category: Analogue and Mixed Signal ICs
News Release from: National Semiconductor | Subject: SCAN25100 CPRI serdes
Edited by the Electronicstalk Editorial Team on 18 September 2006
Serdes enables distributed basestations
National Semiconductor has introduced an advanced serialiser/deserialiser (serdes) for next-generation basestation architectures.
National Semiconductor has introduced an advanced serialiser/deserialiser (serdes) for next-generation basestation architectures National's new CPRI (common public radio interface) serdes is the world's first to guarantee plus or minus 800ps delay calibration measurement accuracy and exceed all CPRI interface signal voltage and jitter requirements
This article was originally published on Electronicstalk on 5 Jan 2001 at 8.00am (UK)
Related stories
Dual-port Gigabit Ethernet transceiver
National Semiconductor has announced the DP83862, a low-cost, highly integrated dual-port 10/100/1000 physical layer transceiver.
World's smallest multifunction supervisory ICs
National Semiconductor has announced a family of supervisory ICs with a variety of factory-programmable features that can be configured in hundreds of possible combinations.
In addition, the SCAN25100 CPRI serdes uses dual onboard phase lock loops (PLLs) to automatically synchronise remote radio heads to the digital processing basestation.
These features enable distributed basestation architectures that use multiple antenna technologies to increase radio efficiency, deployment flexibility, and maximise capacity and coverage, while at the same time lowering backhaul, site property and bandwidth costs.
In addition to next-generation GSM, CDMA, W-CDMA, CDMA2000, WiMAX, TD-SCDMA and other basestation architectures, National's SCAN25100 CPRI serdes is also well-suited for radar, satellite, test equipment, medical imaging, particle accelerator equipment and other high-performance data transfer applications.
Further reading
Leadless leadframe package shrinks LDO
National Semiconductor has introduced a full-featured 500mA LDO regulator for medium-current applications in computing devices and portable products.
Boomer shrinks stereo headphone amplification
New from National Semiconductor, the LM4811 Boomer audio amplifier is a 105mW stereo headphone amplifier for use in 3 and 5V systems requiring a headphone output and volume control.
Frugal dual-channel A/D conversion
National Semiconductor has introduced a dual-channel 8bit A/D convertor with record low-power dissipation levels.
basestation vendors and operators must squeeze more capacity and better coverage out of the existing spectrum to cost-effectively deliver rich data and video mobile broadband content.
Because today's modulation and coding techniques are approaching theoretical capacity limits in the frequency and time domains, vendors and operators are turning to the space domain, or distributed basestation architectures with multiple antennas, to deliver a compelling DSL-like experience to mobile consumers.
Distributed basestation architectures decentralise the radio electronics by moving the radio circuits from the basestation to their respective antennas.
These remote radio heads (RRHs) are a challenge because they introduce interconnect delay and synchronisation issues for the central basestation.
With its patent-pending precision delay calibration measurement (DCM) circuitry and independent transmit and receive PLLs, National's SCAN25100 CPRI serdes accurately measures delays and seamlessly synchronises the RRHs with the central basestation without additional components or complicated system intervention.
A next major step toward improving cellular capacity and coverage at lower per-megabyte cost is to use multi-element beam-steering "smart" antennas and multiple-input, multiple-output (MIMO) antennas within RRHs.
These multiple antenna systems, however, can have even tighter timing requirements.
Calibrating delays between the basestations and these RRHs is difficult to perform accurately using traditional logic approaches.
To track fibre delay changes as small as 200ps, National's SCAN25100 CPRI serdes integrates DCM circuitry to precisely measure basestation-to-RRH and RRH-to-RRH fibre delay components with a guaranteed plus or minus 800ps of accuracy.
This patent-pending DCM circuitry also accurately reports the chips own deterministic latency and measures off-chip system delays as well.
DCM operates transparently and does not interrupt the CPRI data link.
The system software can launch DCM as often as every five milliseconds if required, such as when tracking fibre delay changes over temperature.
National's SCAN25100 will be demonstrated on Booth 506 in Hall A4, at the Electronica trade show in Munich, Germany, from 14th to 17th November 2006.
In addition to the precision delay calibration and independent transmit and receive PLLs, National's 2457.6, 1228.8 and 614.4Mbit/s SCAN25100 CPRI serdes integrates challenging high-speed, mixed-signal and clock management, and conditioning features.
The SCAN25100 includes programmable serial transmit de-emphasis and receive equalisation that exceeds both the CPRI high-voltage and low-voltage standard specifications for jitter and voltage.
The chip also integrates 8b/10b encoding, line code violation, comma detect, lock detect, CPRI loss of signal and loss of frame, serial termination, programmable LVTTL or 1.8V CMOS parallel interface, IEEE 1149.1/6 for JTAG SCAN testability and other functions.
With superior jitter performance, 8kV electrostatic discharge (ESD) and hot-plug protection, the SCAN25100 is an extremely robust interconnect solution for fibre, backplanes and cables more than 15m in length.
As an option, the SCAN12100, a reduced-speed 1228.8 and 614.4Mbit/s version with the same features as the SCAN25100, is also available.
To enable optimal system partitioning, National provides CPRI framer protocol as high-level FPGA code with the SCAN25100 and SCAN12100.
Customisable, high-level code is ready for integration into existing, low-cost FPGAs.
This optimised partitioning integrates the challenging analogue serdes, clocking and DCM functions into the SCAN25100 and SCAN12100 while the reconfigurable FPGA handles the logic functions.
This system partitioning provides the highest jitter and timing performance while future-proofing the system design.
Available now, the SCAN25100 CPRI serdes is priced at $14.60 and the SCAN12100 is priced at $10.05 each in 1000-unit quantities.
• National Semiconductor: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
