Nassda joins Cadence Connections programme

Nassda's HSIM hierarchical full-chip circuit simulator has been integrated into Cadence's analogue design environment.

Nassda's HSIM hierarchical full-chip circuit simulator has been integrated into Cadence's analogue design environment.

With the acceptance of Nassda as a Platinum member of the Cadence Connections programme, Cadence customers will have easier full-chip verification at the transistor level.

"Joining the Cadence Platinum Connections programme enables us to better meet the needs of our common customers who work with huge designs", stated Sang Wang, CEO of Nassda.

"With this close relationship, design teams will now have access to Nassda's full-chip circuit simulator for their complex analogue, mixed-signal, and SoC designs within Cadence's market-leading environment.

We look forward to working closely with Cadence to seek to develop advanced verification technologies that will be of tremendous benefit to designers in the future".

"Working with Nassda gives our customers access to their full-chip verification solution in a tightly integrated environment", stated Charlie Huang, Vice President for Marketing and Business Development, IC Solutions at Cadence.

"Nassda's HSIM product is complementary to our back-end circuit verification flow.

It will be a tremendous aid to engineers involved in nanometer circuit design, helping them verify full-chip pre- and post-layout circuit functionality".

As part of the Platinum Partners Program, Cadence works closely with its partners to analyse, develop and optimise the flow of data between the tools.

Cadence customers will benefit from the tight integration between HSIM and the Cadence environment.

In choosing its Platinum partners, Cadence looks for companies that augment its design methods by providing common customers with easy access to significant emerging products and technologies.

HSIM provides detailed circuit-level analysis of timing and power behaviour, and signal integrity effects.

It solves the critical issue of analysing circuit behaviour while taking into account the electrical and parasitic effects of nanometer scale silicon.

Before the availability of HSIM, design teams were unable to analyse these effects with a tool that had the speed, accuracy and capacity needed for full-chip verification.

The HSIM integration for Cadence's analogue design environment is available immediately.

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