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Product category: Design and Development Software
News Release from: MoSys | Subject: 1T-SRAM memory compiler
Edited by the Electronicstalk Editorial Team on 16 June 2005

Compiler generates SRAM design scenarios

MoSys has released a 1T-SRAM memory compiler for standard 0.13-micron CMOS logic processes

The compiler targets processes from TSMC, Chartered, SMIC and UMC. The MoSys memory compiler is a web-accessible tool that automatically generates a wide variety of design scenarios for MoSys' 1T-SRAM, thereby enabling SoC designers to efficiently evaluate different memory configurations for their designs.

Available in July through the MoSys website, the 0.13-micron compiler gives SoC design engineers complete control when assessing various options and benefits of implementing 1T-SRAM memory technology in their SoC deigns.

The compiler provides front-end design information, such as datasheets, simulation models and timing models for synthesis.

It also allows SoC designers to include specific 1T-SRAM macro instances in their designs by generating place and route views and specifications for memory sizes, configurations, power, speed and temperature ranges.

With this information on hand, all of the views required for simulation, synthesis, floor-planning and place and route of an SoC design are generated, allowing design engineers to quickly explore numerous 'what if' scenarios.

On customer licensing of the specified 1T-SRAM macro design, MoSys delivers the final GDSII database for customer tape out.

The MoSys 1T-SRAM compiler is targeted for both high-speed and low-power designs.

When high speed options are specified, the compiler can produce macros capable of running up to 266MHz with bus widths from 32 to 256bit wide.

High speed macro sizes range from 512Kbit to 4Mbit.

The low power options generate macros capable of achieving standby power of less than 80uA/Mbit, with clock frequencies up to 133MHz and bus widths of 32 or 64bit wide.

Low power macro sizes range from 512Kbit to 4Mbit.

'We are delighted to enable and accelerate our customers' embedded memory SoC designs on aggressive process geometries', stated Karen Lamar, Vice President of Sales and Marketing for MoSys.

'MoSys' new 1T-SRAM compiler is an effective tool to help SoC designers ensure that they are generating the most optimised designs and making the best embedded memory technology selections for their product mix'.

'We strive to make the process of integrating MoSys' technology into new SoCs as efficient as possible'.

With the introduction of the 0.13-micron 1T-SRAM compiler, MoSys now offers customers a wide choice of options in design methodologies that include compiled, full custom and Classic preconfigured memory macros.

The MoSys 0.13-micron 1T-SRAM compiler front-views generator is available now.

The compiler back-end optimiser is scheduled for release in the fourth quarter of 2005.

'The availability of MoSys' 1T-SRAM compilers, which are parametrically coupled with the Classic macros product family, is an invaluable tool for MoSys' customers'.

'The SoC design process is greatly facilitated by use of 1T-SRAM compilers, which allow for specification optimisation, resulting in a quick turn drop-in embedded SRAM memory solution'.

'It's a big cost and time savings for any semiconductor designer', said Rich Wawrzyniak, Senior ASICs and SoC Analyst with Semico Research.

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