News Release from: MoSys
Edited by the Electronicstalk Editorial Team on 8 April 2002
MoSys and TSMC extend collaboration agreement
MoSys and Taiwan Semiconductor Manufacturing Company have extended their long-standing 1T-SRAM collaboration agreement to include the 90nm process node.
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MoSys and Taiwan semiconductor manufacturing Company have extended their long-standing 1T-SRAM collaboration agreement to include the 90nm process node, bringing the industry's smallest bit cells to a broad market. MoSys has already taped-out its 1T-SRAM and 1T-SRAM-R macros optimised for TSMC's 90nm technology. At 0.61um2 (1T-SRAM) and 0.52um2 (1T-SRAM-R), the cells are about half the size of the smallest announced 90nm SRAM cell.
This small cell size enables early availability of 1T-SRAM memory designs with densities of 1.1mm2 per megabit.
Under the agreement, the two companies will work together to offer MoSys' 1T-SRAM designs in TSMC 90nm technology, giving customers practical and cost-effective paths to SoC designs requiring high-density embedded memory.
This latest agreement builds on the companies' partnership on all previous nodes from 0.25-micron to 0.13-micron.
"Our collaboration with MoSys on our 90nm process is consistent with our goal to accelerate the availability of options and value-added IP to the market", said Dr Genda Hu, TSMC vice president of marketing.
"Highly integrated designs require more embedded memory, so we are motivated to bring the smallest available CMOS memory cell into production quickly".
Mark-Eric Jones, vice president of marketing and Intellectual Property at MoSys, added, "We have already proven our 90nm 1T-SRAM bit cell concept at TSMC.
With embedded memory representing the majority of die area on today's SoC designs and increasing every year, designers require the earliest availability of the best high-density embedded memory technology on advanced processes.
It is the single most important enabler for their next generation SoC designs".
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