Product category: Intellectual Property Cores
News Release from: MoSys | Subject: 1T-SRAM-R
Edited by the Electronicstalk Editorial Team on 30 January 2002
Embedded memory cuts hard
and soft error rates
MoSys has released its new 1T-SRAM-R embedded memory technology option for applications that require very high reliability, immunity to soft errors and lowest manufacturing cost
Fabricated in standard logic processes and employing the same, simple, industry-standard SRAM interface, 1T-SRAM-R memory macros can directly replace other embedded SRAMs, achieving lower cost and higher reliability without changes to system design. 1T-SRAM-R memories are the first embedded memories to incorporate Transparent Error Correction (TEC), a MoSys patented technology that eliminates the need for laser repair during manufacture or self-repair at power-up.
This article was originally published on Electronicstalk on 30 January 2002 at 8.00am (UK)
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Transparent Error Correction technology dynamically corrects both hard and soft errors, repairing silicon defects that occurred during as well as after the manufacture of the chip, therefore improving the yield and reliability of devices incorporating 1T-SRAM-R macros.
Transparent Error Correction allows 1T-SRAM-R memories to achieve soft error rates (SER) of less than 10FIT/Mbit in 0.13-micron technology - three orders of magnitude better than traditional SRAMs - resulting in dramatically improved system-level reliability.
"Designers of the next generation of system-on-chip products are being challenged to overcome the rapidly increasing soft error rates of six or four transistor SRAMs in deep submicron processes", commented Mark-Eric Jones, MoSys' vice president and general manager of intellectual property, "Our production-proven 1T-SRAM embedded memory already offers measured soft error rates that are significantly better than other SRAM technologies.
Further reading
High density SRAM for system on chip
A large amount of embedded memory on a competitively priced consumer-oriented SoC will enhance the real-time conference-calling capabilities of mobile phones
Murayama takes on key Japanese market
MoSys has named Takashi Murayama (56) as Vice President and Country Manager, Japan
Going forward, our 1T-SRAM-R option now enables soft error rates to be reduced by a factor of one thousand or more without the 20 to 30% cost penalty required to implement error checking and correction (ECC) circuits for other SRAMs".
Transparent Error Correction achieves these quality and reliability advantages without the traditional die-area and cost penalties associated with ECC, while still meeting standard logic design rules.
By also including all the error correction circuitry within the macro, Transparent Error Correction technology provides the industry-standard SRAM interface and maintains the high performance required by leading-edge applications.
In addition to the proven yield and cost advantages offered by 1T-SRAM technology, Licensees using MoSys' 1T-SRAM-R macros will realise additional product cost savings due to the simplified manufacturing flow that eliminates the need for laser repair.
1T-SRAM-R memory macros are now available for standard logic processes starting with the 0.13-micron generation.
(This was Electronicstalk's Top Story on 30 January 2002)
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