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Product category: Intellectual Property Cores
News Release from: MoSys
Edited by the Electronicstalk Editorial Team on 18 January 2002
MoSys turns to Mentor to reduce memory
test costs
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MoSys and Mentor Graphics are working to qualify and deliver memory built-in self-test (BIST) solutions optimised for the MoSys 1T-SRAM family of high-density embedded memories to reduce test cost.
MoSys and Mentor Graphics are working to qualify and deliver memory built-in self-test (BIST) solutions optimised for the MoSys 1T-SRAM family of high-density embedded memories to reduce test cost MoSys and Mentor have verified the integration of 1T-SRAM embedded memories using the Mentor Graphics) MBISTArchitect and BSDArchitect tool suites for memory BIST and boundary scan, respectively