Product category: Intellectual Property Cores
News Release from: MIPS Technologies
Edited by the Electronicstalk Editorial Team on 23 October 2001
Eureka Technology joins
in MIPS alliance
Eureka Technology has joined the MIPS Alliance Programme (MAP), and has announced the availability of several IP cores designed specifically to support the industry-standard MIPS32 4Kand MIPS64 5K fam
Eureka Technology has joined the MIPS Alliance Programme (MAP), and has announced the availability of several IP cores designed specifically to support the industry-standard MIPS32 4Kand MIPS64 5K families of processor cores. "We are very excited about becoming a member of the MAP programme and the addition of the new IP cores for use in creating new highly-integrated MIPS-based(TM) processors", said Simon Lau, President of Eureka Technology.
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"Eureka Technology has been focusing on SoC design with support for most popular embedded CPUs for a wide range of applications.
These new cores provide risk-free and readily available design solutions to our customers who are using the MIPS processor architecture".
The new IP cores support the MIPS EC interface for embedded processor cores as well as the SysAD bus for compatibility with existing OEM designs using MIPS-based CPUs.
Further reading
Company holds back earnings report
MIPS Technologies is delaying the release of its MIPS third quarter fiscal 2007 earnings, pending a report on its treatment of option grants
Eureka's cores include CPU bus slave, PCI bridge, SDRAM controller, and system controller, which is an all-in-one companion chip to the MIPS processor.
These IP cores support many advanced features of the EC and SysAD interfaces, such as address pipeline and out-of-order execution.
Each of these cores is pre-verified and can be used in a stand-alone format or integrated with other Eureka IP cores for different applications.
These cores are available for licensing in Verilog and VHDL source code format, and in netlist format supporting most popular FPGA and PLD devices.
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