Product category: Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial Team on 17 August 2007
Design companies agree on verification
The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability.
Cadence Design Systems and Mentor Graphics will standardise on a verification methodology based on the IEEEStd 1800-2005 SystemVerilog standard The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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It delivers on the promise of SystemVerilog with established interoperability mechanisms for verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows.
The OVM will include a robust class library and be available in source code format.
Cadence and Mentor have contributed both technology and resources to develop the foundation of the methodology and the libraries.