Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: ADMS 4.0
Edited by the Electronicstalk Editorial Team on 10 February 2004
Mixed-signal verification supports HLLs
Mentor Graphics has enhanced its Advance MS (ADMS) mixed-signal functional verification platform by adding support for SystemVerilog and SystemC languages
ADMS 4.0 also contains expanded tool capabilities that enable designers to verify that their designs are functioning to the original specification in either a digital-centric or analogue-centric design flow. ADMS version 4.0 now delivers full language support for SystemVerilog, SystemC VHDL, Verilog, Spice, VHDL-AMS, Verilog-AMS and C.
This article was originally published on Electronicstalk on 10 February 2004 at 8.00am (UK)
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Support for eight languages gives users the ability to perform block-level validation and full-chip functional verification in a single simulation environment from the system specification stage to the post-layout verification stage.
With ADMS 4.0, Mentor is delivering a single common platform to extend both digital verification and analogue verification for mixed-signal designs.
It enables digital centric verification such as testbenches (directed testing and pseudorandom testing).
It enables analogue-centric verifications such as circuit simulation (DC, AC, transient, parametric, Monte Carlo and corner), and it also enables mixed-signal centric verification such as "checkerboard" analysis.
With this common verification platform, ADMS 4.0 enables concurrent top down design and bottom up verification of AMS SoC designs.
Further reading
Infineon and Chartered use litho-friendly design
Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology
Mixed-signal flow is proved with UWB transceiver
Mentor Graphics has set up a new reference flow for analogue and mixed-signal SoC designs
Functional verification expands in scope
Platform addresses low-power verification and incorporates verification management capabilities that enable closed-loop management reporting, analysis and documentation
ADMS 4.0 also integrates with Verisity SpecMan Elite to facilitate the complex verification strategies required for new mixed-signal designs.
This integration enables early verification of the architectural or partitioning decisions being made, and can be reused as testbenches throughout the design process.
These allow fundamental design flaws to be discovered and then corrected early and easily.
For global companies utilising geographically dispersed design teams, ADMS offers each team the ability to perform block-level verification in their preferred language.
When blocks are brought together for full-chip implementation, including intellectual property (IP) from other sources, ADMS can be used for final, full-chip verification while preserving design elements in their native language.
This alleviates the risk of data compatibility and integrity problems and uncovers functional flaws that can occur when using multiple verification tools.
Additionally, ADMS integrates seamlessly with any design flow, delivering unmatched flexibility regardless of existing tools.
"Advance MS is the original multi-language, multi-level simulator for analogue, mixed-signal and RF designs", said Jue-Hsien Chern, Vice President and General Manager, Deep Submicron Division, Mentor Graphics.
"We've got years of technology research and customer collaboration behind the development of this platform.
With the addition of SystemVerilog and SystemC support, Mentor furthers its leadership position in delivering scalable verification solutions".
Pricing for Advance MS 4.0 starts at US $110,000 in North America, and will be available in Q2, 2004 for Linux, HP and Sun platforms.
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