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Product category: Design and Development Hardware
News Release from: Mentor Graphics UK | Subject: CelaroPro
Edited by the Electronicstalk Editorial Team on 31 January 2003

Next-generation emulator for next-generation SoCs

Note: A free brochure or catalogue is available from Mentor Graphics UK on the products in this news release. Click here to request a copy.

CelaroPro is the new high-capacity verification system from Mentor Graphics for complex system-on-chip designs

CelaroPro is the new high-capacity verification system from Mentor Graphics for complex system-on-chip designs, and the latest addition to the Celaro product family. CelaroPro addresses the challenges of the industry's largest designs by delivering a two to four times increase in capacity and extended support for third-party solutions, while preserving full compatibility with current Celaro products.

A seamless upgrade path to CelaroPro allows customers to optimise their return on investment and maintain a consistent methodology and verification environment.

With an expanded capacity of up to 30 million gates, CelaroPro is Mentor's next generation emulator, featuring the unique CEOS "custom emulation on silicon" architecture, The new emulator offers extended IP support, a faster RTL flow for designs and memories, and integration with third-party EDA tools including TransEDA's VN-Cover and Verisity Specman.

Additionally, support for Verisity eCelerator is scheduled for later this year.

Through its iSolve solutions CelaroPro delivers support for the largest range of IP cores on the market, including cores from ARM, IBM and TI.

These capabilities enable CelaroPro to handle the complex verification challenges in all leading-edge product applications including wireless 3G, HDTV and set top box graphics, multimedia and imaging systems.

"At the heart of the CelaroPro emulator is an industry-breakthrough 83 million transistor chip, developed by Mentor as part of our third-generation set of custom emulation technology chips.

This unique technology allows CelaroPro to deliver a high design capacity per board without compromising on either the emulation performance or design visibility.

Harnessing Mentor's extensive emulation expertise, the custom emulation chip opens the way for future capacity and technology gains in our emulators", said Philippe Vallet, Director of R and D at Mentor's Emulation Division.

Expanding the emulation function beyond pure chip emulation, CelaroPro creates a powerful hardware and software co-verification solution with enhanced functions, including code coverage, testbench acceleration, interactive design debug, and emulation within C-based environments.

Integrations with leading verification tools, including ModelSim, Seamless, NC-Sim and Verisity, give engineers the ability to perform fast and accurate co-simulation tasks in a single systems environment.

Walden C Rhines, Chairman and CEO said, "Everyone is looking for ways to maximise their competitiveness, and cut time to market.

Verification is still proving to be the biggest bottleneck in today's complex SoC design process, yet the one with most time- and cost-saving potential.

The launch of CelaroPro solidifies Mentor's leadership position in the emulation market".

"With CelaroPro and VStation, Mentor has a unique combination of market-leading technologies.

We are committed to supporting and enhancing both product lines to the benefit of our customers, and ultimately will take advantage of the experience and technologies that lie within Mentor to create a revolutionary fourth generation emulation solution", Rhines concluded.

CelaroPro handles multiple methodologies including RTL verification, cosimulation, C-environment comodelling, software validation and virtual prototyping.

CelaroPro also delivers leading performance of up to 2MHz in in-circuit and stand-alone modes, as well as faster compile times, made possible by the new RTL-Pro loader and debugger tools.

RTL-Pro Loader fully handles RTL Verilog, VHDL and mixed-language designs, providing a fast and seamless compile environment within its graphical user interface.

It also eliminates the need for investment and training in synthesis tools.

RTL-Pro Debugger allows users to perform interactive source-level debug, which is fully integrated into CelaroPro's highly productive graphical debug environment.

CelaroPro is a flexible system and can be dynamically partitioned as four independent emulators, and then instantly reconfigured for one very large design, ideally suited to customers who need centralised verification server capability.

It also features an improved streamlined memory modelling technique that supports a faster, highly automated verification process, shortening time to emulation.

For designs containing RTL memories, CelaroPro automatically detects and compiles these memories, thus eliminating the need to create emulation models.

CelaroPro enables engineers to reduce their verification cycles from weeks to literally days, significantly reducing end-product cost and time to market.

(This was Electronicstalk's Top Story on 31 January 2003) Request a free brochure from Mentor Graphics UK....

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