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Product category: Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial Team on 14 March 2002

LSI Logic signs off Mentor's ModelSim

The ModelSim HDL simulation tool has achieved Verilog, VHDL and mixed VHDL Testbench with Verilog gate-level netlist simulation signoff from LSI Logic

Using ModelSim, LSI Logic customers can now simulate application specific integrated circuit (ASIC) designs in VHDL, Verilog or a mix of Verilog netlist with VHDL Testbench. "We have worked closely with Model Technology to make significant enhancements to its simulation tools, which has translated into higher performance, better flexibility and reduced project cycle time for our mutual customers", said Jeff Vanderlip, director of ASIC technical marketing, LSI Logic.

"By qualifying mixed mode simulation, customers are able to move from VHDL to Verilog as the design progresses from RTL to netlist.

Support for multilingual simulation allows VHDL oriented customers to simulate a Verilog netlist with fully accurate timing yet keep testbenches written in high level VHDL".

LSI Logic is a leading designer and manufacturer of SoC designs in the communications, consumer and storage markets for applications that access, interconnect and store data, voice and video.

Its FlexStream design methodology, leading edge process, extensive portfolio of IP and leading edge packaging provides cost-effective, high performance ASIC and SoC solutions.

By certifying ModelSim for use with mixed VHDL testbench and Verilog netlist, LSI Logic customers, such as Ericsson Microwave Systems, can work in a versatile simulation environment that achieves the highest simulation throughput for their designs.

"Model Technology has had a successful six-year relationship with LSI Logic through its support of ModelSim VHDL", said John Lenyo, director of marketing for Model Technology.

"This new commitment strengthens our partnership to provide mutual customers with the ability to easily shift from VHDL to Verilog in the different stages of the design process".

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