Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: IBM SiGe support
Edited by the Electronicstalk Editorial Team on 12 November 2001
Physical verification extended
to SiGe process
Mentor Graphics is developing physical verification tool support for IBM's mixed-signal SiGe family of semiconductor processes
Mentor Graphics is developing physical verification tool support (DRC/LVS) for IBM's mixed-signal SiGe family of semiconductor processes. The IBM SiGe foundry has joined the growing list of silicon foundry service providers whose process technologies are supported by the Mentor Graphics Calibre physical verification toolsuite.
This article was originally published on Electronicstalk on 12 November 2001 at 8.00am (UK)
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As with Mentor's support of IBM's CMOS process family, rule files will be developed by Mentor, qualified by IBM and Mentor, and will be available directly from IBM.
"The addition of Calibre to IBM's SiGe design tool offering reflects a growing customer interest for Mentor's physical verification tools", said Kevin Brelsford, technical marketing manager, IBM Microelectronics.
"The new Calibre rule files are intended to enable joint customers of IBM and Mentor to perform physical verification of mixed-signal SoC designs".
Further reading
Infineon and Chartered use litho-friendly design
Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology
Mixed-signal flow is proved with UWB transceiver
Mentor Graphics has set up a new reference flow for analogue and mixed-signal SoC designs
The Calibre physical verification products provide a high degree of accuracy for analog/mixed-signal designs.
These tools enable designers developing digital and analogue circuits to rapidly verify their components and the complete integrated circuit.
"Historically, some verification tools have been optimised for digital designs while others have worked better for analogue flows.
Our customers' application of Calibre to designs targeting analogue, logic and mixed-signal processes recognises the flow-invariant, physical verification capability enabled by Calibre's design style independence", said Anthony Nicoli, marketing manager for the Calibre business unit.
Calibre's physical verification tool suite, Calibre DRC and Calibre LVS, ensures that IC physical designs conform to foundry manufacturing rules and match the intended functionality of the chip.
Calibre features design style-independent execution to provide optimal performance on designs ranging from RAMs to SoCs using a single, qualified rule file.
Calibre also provides advanced debugging capabilities, including intuitive error reporting, a graphical results viewing environment and hierarchical error isolation.
The combined force of design style independence and advanced debugging extend Calibre's world-class run time performance to further reduce verification time by simplifying tool setup and error correction.
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