Product category: Intellectual Property Cores
News Release from: Mentor Graphics UK | Subject: Inventra IP cores for Altera Excalibur
Edited by the Electronicstalk Editorial Team on 26 October 2001
IP cores add network functions to PLDs
Mentor Graphics has developed a selection of Inventra IP cores optimised for use with Altera's Excalibur ARM-based embedded processor solutions
Mentor Graphics, as a member of the Altera Megafunction Partnership Programme (AMPP), has been developing IP solutions, such as the new Inventra IPX product, that are preoptimised for easy integration into Altera PLDs. Mentor has extended its support to the new Altera Excalibur ARM-based family of devices, enabling the rapid development of system-on-a-programmable-chip (SoPC) applications.
This article was originally published on Electronicstalk on 26 October 2001 at 8.00am (UK)
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The Altera Excalibur ARM-based embedded processor solutions are the first general-purpose devices that combine programmable logic and a high-performance ARM9T processor core.
Mentor Graphics Inventra IP cores are standards-optimised to integrate easily into SoPC designs with embedded microprocessors, such as the ARM-based devices.
The Inventra cores used by Altera's customers are ideal for next-generation networking, mobile communication, computer and consumer products such as residential gateways, mass storage, game consoles, and navigation system applications.
The first cores to be made available from Inventra with wrappers for the ARM bus architecture include: the MUSBFSFC USB 1.
1 full speed function controller; the MCAN2.0 CAN 2.0 network controller; the MI2CV2 I2C V2.0 bus interface; and the M16550S enhanced UART with FIFO and synchronous CPU interface.
Additional communication IP cores from Inventra will be announced to further support and enhance the standards-based IP for Excalibur ARM-based embedded processor solutions.
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