Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: TestKompress
Edited by the Electronicstalk Editorial Team on 03 October 2001

Design for test method cuts ATE
overheads

Mentor Graphics has developed a new patent-pending design-for-test technology that it reckons extends the capacity of ATE for a significant reduction in the cost of semiconductor testing.

Mentor Graphics has developed a new patent-pending design-for-test (DFT) technology called Embedded Deterministic Test (EDT) that it reckons extends the capacity of automatic test equipment for a significant reduction in the cost of semiconductor testing, which can represent as much as 50% of manufacturing costs Mentor's first EDT product, TestKompress, employs the new compression technology that allows semiconductor manufacturers to reduce the ATE memory and time requirements for testing ASIC, IC and SoC designs by up to 10 times